stats: updates due to changes to x86, stale configs.

[gem5.git] / tests / long / se / 50.vortex / ref / arm / linux / simple-timing / config.ini

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 8802837e95910f76a6f66733bc92c3d62b675050..8d05feb2e2d072ae2bc96c02aab0b7a842b84d61 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -10,14 +10,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
@@ -36,24 +38,29 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
+branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
 dtb=system.cpu.dtb
 eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -63,6 +70,7 @@ numThreads=1
 profile=0
 progress_interval=0
 simpoint_start_insts=
+socket_id=0
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -105,10 +113,35 @@ hit_latency=2
 sequential_access=false
 size=262144
 
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
 eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.dtb.walker
 
@@ -116,6 +149,7 @@ walker=system.cpu.dtb.walker
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
 eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -163,24 +197,60 @@ eventq_index=0
 type=ArmISA
 eventq_index=0
 fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
 id_isar3=17899825
 id_isar4=268501314
 id_isar5=0
-id_mmfr0=3
+id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
-id_mmfr3=4027589137
+id_mmfr3=34611729
 id_pfr0=49
-id_pfr1=1
-midr=890224640
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
 children=walker
 eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.itb.walker
 
@@ -188,6 +258,7 @@ walker=system.cpu.itb.walker
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
 eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -228,15 +299,16 @@ sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -251,7 +323,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -261,18 +333,30 @@ ppid=99
 simpoint=0
 system=system
 uid=100
+useArchPT=false
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8