---------- Begin Simulation Statistics ----------
-sim_seconds 1.096187 # Number of seconds simulated
-sim_ticks 1096186990500 # Number of ticks simulated
-final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.150226 # Number of seconds simulated
+sim_ticks 1150225722500 # Number of ticks simulated
+final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 245276 # Simulator instruction rate (inst/s)
-host_op_rate 264248 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 174074375 # Simulator tick rate (ticks/s)
-host_mem_usage 310916 # Number of bytes of host memory used
-host_seconds 6297.23 # Real time elapsed on the host
-sim_insts 1544563087 # Number of instructions simulated
-sim_ops 1664032480 # Number of ops (including micro ops) simulated
+host_inst_rate 267770 # Simulator instruction rate (inst/s)
+host_op_rate 288482 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 199406485 # Simulator tick rate (ticks/s)
+host_mem_usage 271372 # Number of bytes of host memory used
+host_seconds 5768.25 # Real time elapsed on the host
+sim_insts 1544563088 # Number of instructions simulated
+sim_ops 1664032481 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory
-system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2055499 # Number of read requests accepted
-system.physmem.writeReqs 1046381 # Number of write requests accepted
-system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue
-system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2064767 # Number of read requests accepted
+system.physmem.writeReqs 1060156 # Number of write requests accepted
+system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue
+system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 127914 # Per bank write bursts
-system.physmem.perBankRdBursts::1 125107 # Per bank write bursts
-system.physmem.perBankRdBursts::2 122280 # Per bank write bursts
-system.physmem.perBankRdBursts::3 124254 # Per bank write bursts
-system.physmem.perBankRdBursts::4 123262 # Per bank write bursts
-system.physmem.perBankRdBursts::5 123345 # Per bank write bursts
-system.physmem.perBankRdBursts::6 123865 # Per bank write bursts
-system.physmem.perBankRdBursts::7 124190 # Per bank write bursts
-system.physmem.perBankRdBursts::8 131999 # Per bank write bursts
-system.physmem.perBankRdBursts::9 134064 # Per bank write bursts
-system.physmem.perBankRdBursts::10 132428 # Per bank write bursts
-system.physmem.perBankRdBursts::11 133673 # Per bank write bursts
-system.physmem.perBankRdBursts::12 133725 # Per bank write bursts
-system.physmem.perBankRdBursts::13 133862 # Per bank write bursts
-system.physmem.perBankRdBursts::14 129895 # Per bank write bursts
-system.physmem.perBankRdBursts::15 130279 # Per bank write bursts
-system.physmem.perBankWrBursts::0 65789 # Per bank write bursts
-system.physmem.perBankWrBursts::1 64087 # Per bank write bursts
-system.physmem.perBankWrBursts::2 62403 # Per bank write bursts
-system.physmem.perBankWrBursts::3 62885 # Per bank write bursts
-system.physmem.perBankWrBursts::4 62820 # Per bank write bursts
-system.physmem.perBankWrBursts::5 62979 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64285 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65232 # Per bank write bursts
-system.physmem.perBankWrBursts::8 67082 # Per bank write bursts
-system.physmem.perBankWrBursts::9 67588 # Per bank write bursts
-system.physmem.perBankWrBursts::10 67303 # Per bank write bursts
-system.physmem.perBankWrBursts::11 67613 # Per bank write bursts
-system.physmem.perBankWrBursts::12 67020 # Per bank write bursts
-system.physmem.perBankWrBursts::13 67468 # Per bank write bursts
-system.physmem.perBankWrBursts::14 66169 # Per bank write bursts
-system.physmem.perBankWrBursts::15 65633 # Per bank write bursts
+system.physmem.perBankRdBursts::0 128524 # Per bank write bursts
+system.physmem.perBankRdBursts::1 125801 # Per bank write bursts
+system.physmem.perBankRdBursts::2 122666 # Per bank write bursts
+system.physmem.perBankRdBursts::3 124575 # Per bank write bursts
+system.physmem.perBankRdBursts::4 123572 # Per bank write bursts
+system.physmem.perBankRdBursts::5 123680 # Per bank write bursts
+system.physmem.perBankRdBursts::6 124357 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124965 # Per bank write bursts
+system.physmem.perBankRdBursts::8 132488 # Per bank write bursts
+system.physmem.perBankRdBursts::9 134781 # Per bank write bursts
+system.physmem.perBankRdBursts::10 133246 # Per bank write bursts
+system.physmem.perBankRdBursts::11 134508 # Per bank write bursts
+system.physmem.perBankRdBursts::12 134524 # Per bank write bursts
+system.physmem.perBankRdBursts::13 134597 # Per bank write bursts
+system.physmem.perBankRdBursts::14 130537 # Per bank write bursts
+system.physmem.perBankRdBursts::15 130646 # Per bank write bursts
+system.physmem.perBankWrBursts::0 66781 # Per bank write bursts
+system.physmem.perBankWrBursts::1 64940 # Per bank write bursts
+system.physmem.perBankWrBursts::2 63173 # Per bank write bursts
+system.physmem.perBankWrBursts::3 63584 # Per bank write bursts
+system.physmem.perBankWrBursts::4 63558 # Per bank write bursts
+system.physmem.perBankWrBursts::5 63644 # Per bank write bursts
+system.physmem.perBankWrBursts::6 65047 # Per bank write bursts
+system.physmem.perBankWrBursts::7 66059 # Per bank write bursts
+system.physmem.perBankWrBursts::8 67975 # Per bank write bursts
+system.physmem.perBankWrBursts::9 68435 # Per bank write bursts
+system.physmem.perBankWrBursts::10 68155 # Per bank write bursts
+system.physmem.perBankWrBursts::11 68585 # Per bank write bursts
+system.physmem.perBankWrBursts::12 68036 # Per bank write bursts
+system.physmem.perBankWrBursts::13 68532 # Per bank write bursts
+system.physmem.perBankWrBursts::14 67159 # Per bank write bursts
+system.physmem.perBankWrBursts::15 66466 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1096186902500 # Total gap between requests
+system.physmem.totGap 1150225621500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 2055499 # Read request sizes (log2)
+system.physmem.readPktSize::6 2064767 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1046381 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1060156 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads
-system.physmem.totQLat 38533876500 # Total ticks spent queuing
-system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads
+system.physmem.totQLat 59945214750 # Total ticks spent queuing
+system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.41 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes
+system.physmem.busUtil 1.36 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
-system.physmem.readRowHits 777772 # Number of row buffer hits during reads
-system.physmem.writeRowHits 406558 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes
-system.physmem.avgGap 353394.36 # Average gap between requests
-system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states
-system.physmem.memoryStateTime::REF 36603840000 # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 7068978000 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 7417161360 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 3857081250 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 4047062250 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 7754580600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 8267360400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 3307910400 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 3472476480 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 71597111040 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 71597111040 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 413628192720 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 422690389875 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 294876051750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 286926756000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 802089905760 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 804418317405 # Total energy per rank (pJ)
-system.physmem.averagePower::0 731.713906 # Core power per rank (mW)
-system.physmem.averagePower::1 733.838021 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 1255486 # Transaction distribution
-system.membus.trans_dist::ReadResp 1255486 # Transaction distribution
-system.membus.trans_dist::Writeback 1046381 # Transaction distribution
-system.membus.trans_dist::ReadExReq 800013 # Transaction distribution
-system.membus.trans_dist::ReadExResp 800013 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3101880 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3101880 # Request fanout histogram
-system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 239650352 # Number of BP lookups
-system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits
+system.physmem.readRowHits 775403 # Number of row buffer hits during reads
+system.physmem.writeRowHits 420503 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes
+system.physmem.avgGap 368081.27 # Average gap between requests
+system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ)
+system.physmem_0.averagePower 468.667814 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states
+system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ)
+system.physmem_1.averagePower 469.748583 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 240019882 # Number of BP lookups
+system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 232 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 303 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 2192373981 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 2300451445 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1544563087 # Number of instructions committed
-system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 1544563088 # Number of instructions committed
+system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.419414 # CPI: cycles per instruction
-system.cpu.ipc 0.704516 # IPC: instructions per cycle
-system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped
-system.cpu.icache.tags.replacements 29 # number of replacements
-system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks.
+system.cpu.cpi 1.489387 # CPI: cycles per instruction
+system.cpu.ipc 0.671417 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction
+system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
+system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 1664032481 # Class of committed instruction
+system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 9220107 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits
+system.cpu.dcache.overall_hits::total 624493043 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses
+system.cpu.dcache.overall_misses::total 9590309 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks
+system.cpu.dcache.writebacks::total 3670055 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements 33 # number of replacements
+system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits
-system.cpu.icache.overall_hits::total 464861353 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
-system.cpu.icache.overall_misses::total 820 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits
+system.cpu.icache.overall_hits::total 466274661 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses
+system.cpu.icache.overall_misses::total 822 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 91001.216545 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks 33 # number of writebacks
+system.cpu.icache.writebacks::total 33 # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73981000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 73981000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73981000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 73981000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73981000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 73981000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
-system.cpu.l2cache.tags.replacements 2022796 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits
-system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses
-system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements 2032334 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.973384 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1078511 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1078511 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081704 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 6081704 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 7160215 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7160252 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 7160215 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7160252 # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data 812323 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 812323 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251665 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 1251665 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2063988 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2064773 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890834 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1890834 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333369 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 7333369 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9224203 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9225025 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9224203 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9225025 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429611 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.429611 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170681 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks
-system.cpu.l2cache.writebacks::total 1046381 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.writebacks::writebacks 1060156 # number of writebacks
+system.cpu.l2cache.writebacks::total 1060156 # number of writebacks
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 9222736 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits
-system.cpu.dcache.overall_hits::total 624006554 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses
-system.cpu.dcache.overall_misses::total 9576685 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks
-system.cpu.dcache.writebacks::total 3700640 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812323 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 812323 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 2032334 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 1252444 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution
+system.membus.trans_dist::CleanEvict 970949 # Transaction distribution
+system.membus.trans_dist::ReadExReq 812323 # Transaction distribution
+system.membus.trans_dist::ReadExResp 812323 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 2064767 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 2064767 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff