---------- Begin Simulation Statistics ----------
-sim_seconds 5.923548 # Number of seconds simulated
-sim_ticks 5923548078000 # Number of ticks simulated
-final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.882581 # Number of seconds simulated
+sim_ticks 5882580526000 # Number of ticks simulated
+final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1176749 # Simulator instruction rate (inst/s)
-host_tick_rate 1487248019 # Simulator tick rate (ticks/s)
-host_mem_usage 213688 # Number of bytes of host memory used
-host_seconds 3982.89 # Real time elapsed on the host
-sim_insts 4686862651 # Number of instructions simulated
-system.physmem.bytes_read 173910080 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 75176384 # Number of bytes written to this memory
-system.physmem.num_reads 2717345 # Number of read requests responded to by this memory
-system.physmem.num_writes 1174631 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 548624 # Simulator instruction rate (inst/s)
+host_op_rate 854806 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1072884756 # Simulator tick rate (ticks/s)
+host_mem_usage 295308 # Number of bytes of host memory used
+host_seconds 5482.96 # Real time elapsed on the host
+sim_insts 3008081022 # Number of instructions simulated
+sim_ops 4686862596 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 11847096156 # number of cpu cycles simulated
+system.cpu.numCycles 11765161052 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 4686862651 # Number of instructions executed
-system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
+system.cpu.committedInsts 3008081022 # Number of instructions committed
+system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4686862580 # number of integer instructions
+system.cpu.num_func_calls 33534539 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4686862527 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
+system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1677713086 # number of memory refs
-system.cpu.num_load_insts 1239184749 # Number of load instructions
-system.cpu.num_store_insts 438528337 # Number of store instructions
+system.cpu.num_mem_refs 1677713084 # number of memory refs
+system.cpu.num_load_insts 1239184746 # Number of load instructions
+system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
+system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
-system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
-system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use
+system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
-system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 4013232252 # number of overall hits
-system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
-system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 675 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
+system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
+system.cpu.icache.overall_misses::total 675 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 1926197 # number of replacements
+system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks
+system.cpu.l2cache.writebacks::total 1018421 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
-system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits
-system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 1668600409 # number of overall hits
-system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
-system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 9112677 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
+system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
+system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
+system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 3053391 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
+system.cpu.dcache.writebacks::total 3697956 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2706631 # number of replacements
-system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 6396007 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 2717345 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 1174631 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff