---------- Begin Simulation Statistics ----------
-sim_seconds 5.901049 # Number of seconds simulated
-sim_ticks 5901048883000 # Number of ticks simulated
-final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.882581 # Number of seconds simulated
+sim_ticks 5882580526000 # Number of ticks simulated
+final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 582820 # Simulator instruction rate (inst/s)
-host_op_rate 908086 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1143336514 # Simulator tick rate (ticks/s)
-host_mem_usage 274832 # Number of bytes of host memory used
-host_seconds 5161.25 # Real time elapsed on the host
+host_inst_rate 548624 # Simulator instruction rate (inst/s)
+host_op_rate 854806 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1072884756 # Simulator tick rate (ticks/s)
+host_mem_usage 295308 # Number of bytes of host memory used
+host_seconds 5482.96 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862594 # Number of ops (including micro ops) simulated
+sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
-system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
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-system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 11802097766 # number of cpu cycles simulated
+system.cpu.numCycles 11765161052 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_fp_insts 0 # number of float instructions
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-system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
+system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1677713082 # number of memory refs
-system.cpu.num_load_insts 1239184745 # Number of load instructions
-system.cpu.num_store_insts 438528337 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
-system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use
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system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
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system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
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system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1053029 # number of writebacks
-system.cpu.l2cache.writebacks::total 1053029 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1382715 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1383390 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789841 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 789841 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2172556 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2173231 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308600000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335600000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593640000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593640000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902240000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 86929240000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902240000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 86929240000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff