stats: update for O3 changes

[gem5.git] / tests / long / se / 70.twolf / ref / alpha / tru64 / o3-timing / config.ini

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 78509c3e80dd31c9c0395aa8ffc2e86ff628a6e6..104ffdb5246f3a06c23db29aff9c7bdc09bebd9d 100644 (file)
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -18,6 +18,7 @@ eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
@@ -115,6 +116,7 @@ smtLSQThreshold=100
 smtNumFetchingThreads=1
 smtROBPolicy=Partitioned
 smtROBThreshold=100
+socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
@@ -599,7 +601,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -628,9 +630,9 @@ master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
 activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -641,27 +643,33 @@ device_rowbuffer_size=1024
 devices_per_rank=8
 eventq_index=0
 in_addr_map=true
+max_accesses_per_row=16
 mem_sched_policy=frfcfs
+min_writes_per_switch=16
 null=false
-page_policy=open
+page_policy=open_adaptive
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCK=1250
 tCL=13750
 tRAS=35000
 tRCD=13750
 tREFI=7800000
-tRFC=300000
+tRFC=260000
 tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
 tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
 port=system.membus.master[0]
 
 [system.voltage_domain]