arch: Fix VecReg container alignement to 128bits view

[gem5.git] / tests / long / se / 70.twolf / ref / arm / linux / o3-timing / simerr

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index e45cd058f745304620a760ededf84001c2ace239..9acbe6defd51852ed7ca9d35cbe435782e69fdfb 100755 (executable)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,5 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.