sim_ticks 250960631000 # Number of ticks simulated
final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1263573 # Simulator instruction rate (inst/s)
-host_tick_rate 1432520595 # Simulator tick rate (ticks/s)
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-host_seconds 175.19 # Real time elapsed on the host
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system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 501921262 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 221363018 # Number of instructions executed
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system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339607 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
-system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
+system.cpu.num_int_register_reads 705008823 # number of times the integer registers were read
+system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165306 # number of memory refs
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
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-system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
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-system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 39420.856412 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff