proc_arst: Add special-casing of clock signal in conditionals.

[yosys.git] / tests / opt / opt_lut.ys

diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 59b12c3511544f7c20351948f0110e9606f686b5..a9fccbb624c05e4d47e0baf73573977396025abd 100644 (file)
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,4 +1,2 @@
 read_verilog opt_lut.v
-synth_ice40
-ice40_unlut
-equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40