---------- Begin Simulation Statistics ----------
-host_inst_rate 828053 # Simulator instruction rate (inst/s)
-host_mem_usage 274124 # Number of bytes of host memory used
-host_seconds 67.88 # Real time elapsed on the host
-host_tick_rate 28436098912 # Simulator tick rate (ticks/s)
+sim_seconds 1.915549 # Number of seconds simulated
+sim_ticks 1915548867000 # Number of ticks simulated
+final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 56205703 # Number of instructions simulated
-sim_seconds 1.930165 # Number of seconds simulated
-sim_ticks 1930164593000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15048990 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 33777.675695 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 13577961 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.097749 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15048990 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 33777.675695 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 13577961 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13577961 # number of overall hits
-system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.097749 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 1471029 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 1471029 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.097749 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1391606 # number of replacements
-system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 430459 # number of writebacks
-system.cpu.dtb.data_accesses 1020784 # DTB accesses
-system.cpu.dtb.data_acv 367 # DTB access violations
-system.cpu.dtb.data_hits 15429793 # DTB hits
-system.cpu.dtb.data_misses 11466 # DTB misses
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.fetch_acv 0 # ITB acv
+host_inst_rate 1659827 # Simulator instruction rate (inst/s)
+host_tick_rate 56637748152 # Simulator tick rate (ticks/s)
+host_mem_usage 290988 # Number of bytes of host memory used
+host_seconds 33.82 # Real time elapsed on the host
+sim_insts 56137087 # Number of instructions simulated
+system.physmem.bytes_read 29663360 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10122368 # Number of bytes written to this memory
+system.physmem.num_reads 463490 # Number of read requests responded to by this memory
+system.physmem.num_writes 158162 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 389289 # number of replacements
+system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
+system.l2c.total_refs 2311163 # Total number of references to valid blocks.
+system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
+system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context
+system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 1710461 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
+system.l2c.Writeback_hits::0 826671 # number of Writeback hits
+system.l2c.Writeback_hits::total 826671 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 6 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0 185878 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
+system.l2c.demand_hits::0 1896339 # number of demand (read+write) hits
+system.l2c.demand_hits::1 0 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
+system.l2c.overall_hits::0 1896339 # number of overall hits
+system.l2c.overall_hits::1 0 # number of overall hits
+system.l2c.overall_hits::total 1896339 # number of overall hits
+system.l2c.ReadReq_misses::0 304138 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 7 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0 118294 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
+system.l2c.demand_misses::0 422432 # number of demand (read+write) misses
+system.l2c.demand_misses::1 0 # number of demand (read+write) misses
+system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
+system.l2c.overall_misses::0 422432 # number of overall misses
+system.l2c.overall_misses::1 0 # number of overall misses
+system.l2c.overall_misses::total 422432 # number of overall misses
+system.l2c.ReadReq_miss_latency 15820206500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 248000 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 6151753000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 21971959500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 21971959500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 2014599 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 826671 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 304172 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 2318771 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.150967 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.538462 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.388905 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.182179 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.182179 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 52016.540189 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52003.930884 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0 52013.009194 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
+system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 52013.009194 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
+system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 116650 # number of writebacks
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses 304138 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 118294 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 422432 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 422432 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency 12170545000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 320000 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 4732225000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 16902770000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 16902770000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 1083819500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 1856492500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.150967 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.538462 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.388905 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0 0.182179 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.182179 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 41685 # number of replacements
+system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context
+system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
+system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
+system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 41725 # number of overall misses
+system.iocache.overall_misses::total 41725 # number of overall misses
+system.iocache.ReadReq_miss_latency 19940998 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency 5722300806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency 5742241804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 5742241804 # number of overall miss cycles
+system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115265.884393 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137714.208847 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137621.133709 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137621.133709 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 41512 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.ReadReq_mshr_miss_latency 10944998 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3561447990 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3572392988 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 3572392988 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 728853 # DTB read accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 9057511 # DTB read hits
+system.cpu.dtb.read_misses 10312 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9069700 # DTB read hits
-system.cpu.dtb.read_misses 10324 # DTB read misses
-system.cpu.dtb.write_accesses 291931 # DTB write accesses
+system.cpu.dtb.read_accesses 728817 # DTB read accesses
+system.cpu.dtb.write_hits 6352446 # DTB write hits
+system.cpu.dtb.write_misses 1140 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6360093 # DTB write hits
-system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 56217537 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 56217537 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14711.221983 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 55286436 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 55286436 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.016562 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 931101 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.016562 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 56217537 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 56217537 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14711.221983 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 55286436 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 55286436 # number of overall hits
-system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.016562 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 931101 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 931101 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 930429 # number of replacements
-system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use
-system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0.929209 # Percentage of idle cycles
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 4982987 # ITB accesses
+system.cpu.dtb.write_accesses 291929 # DTB write accesses
+system.cpu.dtb.data_hits 15409957 # DTB hits
+system.cpu.dtb.data_misses 11452 # DTB misses
+system.cpu.dtb.data_acv 367 # DTB access violations
+system.cpu.dtb.data_accesses 1020746 # DTB accesses
+system.cpu.itb.fetch_hits 4973520 # ITB hits
+system.cpu.itb.fetch_misses 4997 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_hits 4977977 # ITB hits
-system.cpu.itb.fetch_misses 5010 # ITB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.fetch_accesses 4978517 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4171 2.16% 2.16% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
-system.cpu.kern.callpal::wrent 7 0.00% 2.19% # number of callpals executed
-system.cpu.kern.callpal::swpipl 176257 91.22% 93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps 6844 3.54% 96.95% # number of callpals executed
-system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::rti 5169 2.68% 99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
-system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 193221 # number of callpals executed
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.numCycles 3831097734 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 56137087 # Number of instructions executed
+system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
+system.cpu.num_func_calls 1482242 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
+system.cpu.num_int_insts 52011214 # number of integer instructions
+system.cpu.num_fp_insts 324192 # number of float instructions
+system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
+system.cpu.num_mem_refs 15462519 # number of memory refs
+system.cpu.num_load_insts 9094324 # Number of load instructions
+system.cpu.num_store_insts 6368195 # Number of store instructions
+system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
+system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
+system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0 75001 40.87% 40.87% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21 131 0.07% 40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1944 1.06% 42.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106426 58.00% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 96331500 0.00% 96.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 565310500 0.03% 96.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel 1911
-system.cpu.kern.mode_good::user 1744
-system.cpu.kern.mode_good::idle 167
-system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1744 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5539986000 0.29% 2.80% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4172 # number of times the context was actually changed
+system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
-system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles
-system.cpu.numCycles 3860329186 # number of cpu cycles simulated
-system.cpu.num_insts 56205703 # Number of instructions executed
-system.cpu.num_refs 15677891 # Number of memory references
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115254.323699 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 41725 # number of overall misses
-system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 41685 # number of replacements
-system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.353399 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 126223 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 126223 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 52001.810288 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 126223 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 126223 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 430459 # number of Writeback hits
-system.l2c.Writeback_hits::total 430459 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 4.436562 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
-system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
-system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits
-system.l2c.demand_hits::1 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 612229 # number of demand (read+write) misses
-system.l2c.demand_misses::1 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 612229 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context
-system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
-system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1710971 # number of overall hits
-system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1710971 # number of overall hits
-system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 612229 # number of overall misses
-system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 612229 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 394928 # number of replacements
-system.l2c.sampled_refs 425903 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use
-system.l2c.total_refs 1889545 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119060 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
+system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
+system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
+system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
+system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
+system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
+system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
+system.cpu.kern.callpal::total 192868 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
+system.cpu.kern.mode_good::kernel 1906
+system.cpu.kern.mode_good::user 1738
+system.cpu.kern.mode_good::idle 168
+system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4174 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.cpu.icache.replacements 927683 # number of replacements
+system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
+system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0 55220553 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
+system.cpu.icache.demand_hits::0 55220553 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0 55220553 # number of overall hits
+system.cpu.icache.overall_hits::1 0 # number of overall hits
+system.cpu.icache.overall_hits::total 55220553 # number of overall hits
+system.cpu.icache.ReadReq_misses::0 928354 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
+system.cpu.icache.demand_misses::0 928354 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0 928354 # number of overall misses
+system.cpu.icache.overall_misses::1 0 # number of overall misses
+system.cpu.icache.overall_misses::total 928354 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 13616370500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 13616370500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 13616370500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0 56148907 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0 56148907 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0 0.016534 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0 0.016534 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::0 0.016534 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14667.218001 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14667.218001 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 85 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 928354 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 928354 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 928354 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10830625500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 10830625500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 10830625500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016534 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::0 0.016534 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::0 0.016534 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1390115 # number of replacements
+system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0 7807536 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0 5848554 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0 183025 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0 199203 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0 13656090 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0 13656090 # number of overall hits
+system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
+system.cpu.dcache.ReadReq_misses::0 1069110 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0 304335 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0 17201 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0 1373445 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0 1373445 # number of overall misses
+system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 27121920500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 9228484000 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 245980000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 36350404500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 36350404500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0 8876646 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0 6152889 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0 200226 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 199203 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 15029535 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.120441 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.049462 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085908 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.091383 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0 0.091383 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 26466.589124 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 26466.589124 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 826586 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 1069110 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 304335 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses 17201 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 1373445 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 1373445 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 23914545000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 8315479000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 194377000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 32230024000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 32230024000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1199607500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 2062370500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120441 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.049462 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.085908 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0 0.091383 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0.091383 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff