---------- Begin Simulation Statistics ----------
sim_seconds 1.829332 # Number of seconds simulated
-sim_ticks 1829332258000 # Number of ticks simulated
-final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1829332014500 # Number of ticks simulated
+final_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4111639 # Simulator instruction rate (inst/s)
-host_op_rate 4111633 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 125278906724 # Simulator tick rate (ticks/s)
-host_mem_usage 291412 # Number of bytes of host memory used
-host_seconds 14.60 # Real time elapsed on the host
-sim_insts 60038305 # Number of instructions simulated
-sim_ops 60038305 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 71650816 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10156864 # Number of bytes written to this memory
-system.physmem.num_reads 1119544 # Number of read requests responded to by this memory
-system.physmem.num_writes 158701 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 1045877 # number of replacements
-system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use
-system.l2c.total_refs 2291835 # Total number of references to valid blocks.
-system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks.
-system.l2c.avg_refs 2.126306 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits
-system.l2c.Writeback_hits::total 825291 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst 905267 # number of overall hits
-system.l2c.overall_hits::cpu.data 979511 # number of overall hits
-system.l2c.overall_hits::total 1884778 # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst 14936 # number of overall misses
-system.l2c.overall_misses::cpu.data 1063552 # number of overall misses
-system.l2c.overall_misses::total 1078488 # number of overall misses
-system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 117189 # number of writebacks
-system.l2c.writebacks::total 117189 # number of writebacks
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41686 # number of replacements
-system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
-system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
-system.iocache.overall_misses::total 41726 # number of overall misses
-system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 41512 # number of writebacks
-system.iocache.writebacks::total 41512 # number of writebacks
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+host_inst_rate 3082632 # Simulator instruction rate (inst/s)
+host_op_rate 3082630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 93925630949 # Simulator tick rate (ticks/s)
+host_mem_usage 334080 # Number of bytes of host memory used
+host_seconds 19.48 # Real time elapsed on the host
+sim_insts 60038469 # Number of instructions simulated
+sim_ops 60038469 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9710427 # DTB read hits
+system.cpu.dtb.read_hits 9710423 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6352498 # DTB write hits
+system.cpu.dtb.write_hits 6352496 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 16062925 # DTB hits
+system.cpu.dtb.data_hits 16062919 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
-system.cpu.itb.fetch_hits 4974648 # ITB hits
+system.cpu.itb.fetch_hits 4974637 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979654 # ITB accesses
+system.cpu.itb.fetch_accesses 4979643 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3658664408 # number of cpu cycles simulated
+system.cpu.numPwrStateTransitions 12714 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 3658670387 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60038305 # Number of instructions committed
-system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
-system.cpu.num_func_calls 1484182 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
-system.cpu.num_int_insts 55913521 # number of integer instructions
-system.cpu.num_fp_insts 324460 # number of float instructions
-system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
-system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
-system.cpu.num_mem_refs 16115709 # number of memory refs
-system.cpu.num_load_insts 9747513 # Number of load instructions
-system.cpu.num_store_insts 6368196 # Number of store instructions
-system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
-system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
-system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
-system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
-system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
-system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
-system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
-system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
-system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
-system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
-system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
-system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
-system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
-system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
-system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
-system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
-system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
-system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
-system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
-system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
-system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
-system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
-system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
-system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
-system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
-system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
-system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
-system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
-system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
-system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
-system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
-system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.kern.syscall::total 326 # number of syscalls executed
+system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192180 # number of callpals executed
+system.cpu.kern.callpal::total 192179 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1909
-system.cpu.kern.mode_good::user 1738
+system.cpu.kern.mode_good::kernel 1908
+system.cpu.kern.mode_good::user 1737
system.cpu.kern.mode_good::idle 171
-system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu.committedInsts 60038469 # Number of instructions committed
+system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
+system.cpu.num_func_calls 1484182 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
+system.cpu.num_int_insts 55913692 # number of integer instructions
+system.cpu.num_fp_insts 324460 # number of float instructions
+system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
+system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
+system.cpu.num_mem_refs 16115703 # number of memory refs
+system.cpu.num_load_insts 9747509 # Number of load instructions
+system.cpu.num_store_insts 6368194 # Number of store instructions
+system.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles
+system.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles
+system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
+system.cpu.Branches 9064428 # Number of branches fetched
+system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
+system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
+system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
+system.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction
+system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
+system.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
+system.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction
+system.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction
+system.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction
+system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction
+system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 60050307 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 2042708 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
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+system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
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+system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.dcache.writebacks::total 833476 # number of writebacks
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+system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id
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+system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits
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+system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits
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+system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits
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+system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits
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+system.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits
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+system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
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+system.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses
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+system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses
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+system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
+system.cpu.l2cache.writebacks::total 74359 # number of writebacks
+system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 993442 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
+system.iobus.trans_dist::WriteResp 51390 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements 41686 # number of replacements
+system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 375534 # Number of tag accesses
+system.iocache.tags.data_accesses 375534 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
+system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
+system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
+system.iocache.overall_misses::total 41726 # number of overall misses
+system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
+system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.writebacks::writebacks 41512 # number of writebacks
+system.iocache.writebacks::total 41512 # number of writebacks
+system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq 7184 # Transaction distribution
+system.membus.trans_dist::ReadResp 948291 # Transaction distribution
+system.membus.trans_dist::WriteReq 9838 # Transaction distribution
+system.membus.trans_dist::WriteResp 9838 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution
+system.membus.trans_dist::CleanEvict 917188 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 133 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 133 # Transaction distribution
+system.membus.trans_dist::ReadExReq 116925 # Transaction distribution
+system.membus.trans_dist::ReadExResp 116925 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
+system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 2149798 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.000529 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram
+system.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 2149798 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 919594 # number of replacements
-system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
-system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
-system.cpu.icache.overall_hits::total 59129922 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
-system.cpu.icache.overall_misses::total 920221 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 108 # number of writebacks
-system.cpu.icache.writebacks::total 108 # number of writebacks
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042700 # number of replacements
-system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655994 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses
-system.cpu.dcache.overall_misses::total 2026067 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks
-system.cpu.dcache.writebacks::total 825183 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff