sim_ticks 1870335522500 # Number of ticks simulated
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 63154034 # Number of instructions simulated
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
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-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
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system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
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system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
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system.iocache.overall_misses::total 41727 # number of overall misses
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system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
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system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
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system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
+system.cpu0.numCycles 3740671046 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
system.cpu0.num_mem_refs 15135515 # number of memory refs
system.cpu0.num_load_insts 9184477 # Number of load instructions
system.cpu0.num_store_insts 5951038 # Number of store instructions
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system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
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system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
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system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
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system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
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system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
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system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
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system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
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system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
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system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
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system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
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+system.toL2Bus.throughput 131930255 # Throughput (bytes/s)
+system.toL2Bus.data_through_bus 246743474 # Total data (bytes)
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+system.iobus.throughput 1460501 # Throughput (bytes/s)
+system.iobus.data_through_bus 2731626 # Total data (bytes)
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system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
system.cpu1.num_func_calls 182742 # number of times a function call or return occured
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
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system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
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system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::1 0 # number of overall misses
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system.cpu1.icache.overall_misses::total 103630 # number of overall misses
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-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses
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system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses
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system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 15 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
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-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 62338 # number of replacements
-system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 707444 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 15613 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 1816759 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 1816759 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 25861 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 732 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 67511 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 67511 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 67511 # number of overall misses
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.tags.replacements 62044 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 7735310 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 7735310 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 67292 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses)
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system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses)
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system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses
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+system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.035266 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044784 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.035829 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
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+system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 39996 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks
+system.cpu1.dcache.writebacks::total 41012 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff