sim_ticks 2332316587000 # Number of ticks simulated
final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1979884 # Simulator instruction rate (inst/s)
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-host_seconds 29.93 # Real time elapsed on the host
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+host_inst_rate 1994377 # Simulator instruction rate (inst/s)
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system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor
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system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14940566 # DTB read hits
+system.cpu.dtb.read_hits 14940568 # DTB read hits
system.cpu.dtb.read_misses 7288 # DTB read misses
-system.cpu.dtb.write_hits 11198205 # DTB write hits
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system.cpu.dtb.write_misses 2199 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 14947854 # DTB read accesses
-system.cpu.dtb.write_accesses 11200404 # DTB write accesses
+system.cpu.dtb.read_accesses 14947856 # DTB read accesses
+system.cpu.dtb.write_accesses 11200405 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26138771 # DTB hits
+system.cpu.dtb.hits 26138774 # DTB hits
system.cpu.dtb.misses 9487 # DTB misses
-system.cpu.dtb.accesses 26148258 # DTB accesses
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system.cpu.itb.inst_misses 4471 # ITB inst misses
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system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
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-system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
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-system.cpu.itb.accesses 60278360 # DTB accesses
+system.cpu.itb.accesses 60278380 # DTB accesses
system.cpu.numCycles 4664556206 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_fp_insts 10269 # number of float instructions
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system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
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system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
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system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 622134 # number of replacements
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projects / gem5.git / blobdiff