stats: update stats to after GPU checkin
[gem5.git] / tests / quick / se / 00.hello / ref / alpha / linux / minor-timing / stats.txt
index a15c23d57cd30272e006a01079a5e848ea3c4cb6..8f96a67eec43e2b14fc3cba6458a788fbb17203d 100644 (file)
@@ -1,30 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000035                       # Number of seconds simulated
-sim_ticks                                    35024500                       # Number of ticks simulated
-final_tick                                   35024500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000038                       # Number of seconds simulated
+sim_ticks                                    37553000                       # Number of ticks simulated
+final_tick                                   37553000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72507                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72491                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              396631772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236200                       # Number of bytes of host memory used
+host_inst_rate                                  69445                       # Simulator instruction rate (inst/s)
+host_op_rate                                    69425                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              407253641                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231420                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             34112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             23296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             10816                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                34112                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        23296                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           23296                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                364                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            973946809                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               973946809                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       665134406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          665134406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           973946809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              973946809                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            620349905                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            288019599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               908369504                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       620349905                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          620349905                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           620349905                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           288019599                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              908369504                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           533                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        34926000                       # Total gap between requests
+system.physmem.totGap                        37448500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -86,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        89                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       443                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        85                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -182,118 +186,100 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           90                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      365.511111                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     232.220198                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.209697                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             22     24.44%     24.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           24     26.67%     51.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           10     11.11%     62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8      8.89%     71.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      4.44%     75.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            7      7.78%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            1      1.11%     84.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            4      4.44%     88.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     11.11%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             90                       # Bytes accessed per row activation
-system.physmem.totQLat                        3928000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13921750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples           84                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             384                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     247.290862                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.108272                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             20     23.81%     23.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           19     22.62%     46.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           10     11.90%     58.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           11     13.10%     71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      2.38%     73.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            5      5.95%     79.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      3.57%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            6      7.14%     90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            8      9.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             84                       # Bytes accessed per row activation
+system.physmem.totQLat                        3307750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13301500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7369.61                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6205.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26119.61                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         973.95                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24955.91                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         908.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      973.95                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      908.37                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.61                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.61                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.10                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        435                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        437                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        65527.20                       # Average gap between requests
-system.physmem.pageHitRate                      81.61                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
-system.physmem.memoryStateTime::REF           1040000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          30394500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    257040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    385560                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    140250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                    210375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                  2082600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  1677000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              21425445                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              20168595                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 67500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1               1170000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                26007075                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                25645770                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             827.295718                       # Core power per rank (mW)
-system.physmem.averagePower::1             815.802457                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 460                       # Transaction distribution
-system.membus.trans_dist::ReadResp                460                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   34112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               533                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     533    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 533                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              618000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4976250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             14.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    1959                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1201                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1551                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     381                       # Number of BTB hits
+system.physmem.avgGap                        70259.85                       # Average gap between requests
+system.physmem.pageHitRate                      81.99                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                     226800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     123750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2043600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               21178350                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 265500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 25872240                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              823.825505                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         346000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        30032750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     347760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     189750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1552200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               20535390                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 831750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 25491090                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              811.591993                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        1333500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        29134000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu.branchPred.lookups                    1929                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1187                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               360                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1557                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     398                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             24.564797                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             25.561978                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     224                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1368                       # DTB read hits
+system.cpu.dtb.read_hits                         1369                       # DTB read hits
 system.cpu.dtb.read_misses                         11                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1379                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1380                       # DTB read accesses
 system.cpu.dtb.write_hits                         884                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     887                       # DTB write accesses
-system.cpu.dtb.data_hits                         2252                       # DTB hits
+system.cpu.dtb.data_hits                         2253                       # DTB hits
 system.cpu.dtb.data_misses                         14                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2266                       # DTB accesses
-system.cpu.itb.fetch_hits                        2630                       # ITB hits
+system.cpu.dtb.data_accesses                     2267                       # DTB accesses
+system.cpu.itb.fetch_hits                        2651                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2647                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2668                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -307,68 +293,180 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            70049                       # number of cpu cycles simulated
+system.cpu.numCycles                            75106                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6400                       # Number of instructions committed
 system.cpu.committedOps                          6400                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                          1118                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                          1085                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              10.945156                       # CPI: cycles per instruction
-system.cpu.ipc                               0.091365                       # IPC: instructions per cycle
-system.cpu.tickCycles                           12515                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           57534                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              11.735312                       # CPI: cycles per instruction
+system.cpu.ipc                               0.085213                       # IPC: instructions per cycle
+system.cpu.tickCycles                           12517                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           62589                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           103.920661                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1972                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.668639                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.920661                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025371                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025371                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4567                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4567                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1232                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1232                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1972                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1972                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1972                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1972                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          227                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          227                       # number of overall misses
+system.cpu.dcache.overall_misses::total           227                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8311500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8311500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      9136500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      9136500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     17448000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     17448000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     17448000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     17448000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2199                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2199                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2199                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2199                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076462                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076462                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.103229                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.103229                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.103229                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.103229                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        73092                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        73092                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76863.436123                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76863.436123                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           58                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7818500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7818500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5371500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5371500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13190000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13190000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13190000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13190000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071964                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071964                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076853                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.076853                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076853                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076853                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           176.176418                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2265                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           175.815240                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2286                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.205479                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.263014                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   176.176418                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.086024                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.086024                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   175.815240                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085847                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085847                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5625                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5625                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         2265                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2265                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2265                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2265                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2265                       # number of overall hits
-system.cpu.icache.overall_hits::total            2265                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5667                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5667                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         2286                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2286                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2286                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2286                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2286                       # number of overall hits
+system.cpu.icache.overall_hits::total            2286                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
 system.cpu.icache.overall_misses::total           365                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25941750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25941750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25941750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25941750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25941750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25941750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2630                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2630                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2630                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2630                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138783                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.138783                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.138783                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.138783                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.138783                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.138783                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71073.287671                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71073.287671                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     27932500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     27932500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     27932500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     27932500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     27932500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     27932500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2651                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2651                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2651                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2651                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2651                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2651                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.137684                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.137684                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.137684                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.137684                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.137684                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.137684                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76527.397260                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76527.397260                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -383,114 +481,108 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          365
 system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25054250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25054250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25054250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25054250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25054250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25054250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138783                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138783                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138783                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27567500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     27567500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27567500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     27567500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27567500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     27567500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.137684                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.137684                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.137684                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.137684                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.137684                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.137684                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              34176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          534                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                534    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            534                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        626250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        279000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          233.917543                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          233.452540                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.917543                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007139                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007139                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   175.828674                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.623866                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005366                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001759                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007124                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014038                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4805                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4805                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          460                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          460                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          533                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          364                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          364                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data           96                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total           96                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          169                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          533                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          364                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31726750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     31726750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5065000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5065000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     36791750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     36791750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     36791750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     36791750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          461                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          461                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5261000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5261000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27008000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     27008000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7673000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      7673000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27008000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12934000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     39942000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27008000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12934000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     39942000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          534                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          365                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          365                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           96                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total           96                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          365                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          169                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          534                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          534                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          365                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          169                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          534                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.997831                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997831                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.998127                       # miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.997260                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.997260                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.997260                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.998127                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997260                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -499,150 +591,112 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          533                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          364                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          364                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           96                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total           96                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          364                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          533                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          533                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25964750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25964750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30112250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30112250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30112250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30112250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997831                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4531000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4531000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     23368000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     23368000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6713000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6713000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23368000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11244000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     34612000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23368000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11244000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     34612000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.997260                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           104.075920                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1968                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.644970                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   104.075920                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.025409                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025409                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4559                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4559                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst         1228                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1228                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst          740                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst          1968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1968                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst         1968                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1968                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst          102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst          125                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst          227                       # number of overall misses
-system.cpu.dcache.overall_misses::total           227                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7718250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7718250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8705750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8705750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst     16424000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16424000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst     16424000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16424000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1330                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1330                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst         2195                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2195                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst         2195                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2195                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.076692                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076692                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.103417                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.103417                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.103417                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.103417                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69646                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        69646                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72352.422907                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72352.422907                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst           58                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst          169                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7145500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7145500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5139500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5139500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12285000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12285000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.072180                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.072180                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076993                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076993                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.snoop_filter.tot_requests          534                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          365                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq           96                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              34176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          534                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001873                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.043274                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                533     99.81%     99.81% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  1      0.19%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            534                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        547500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        253500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp                460                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           460                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   34112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               533                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     533    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 533                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              602500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2833000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------