---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
-sim_ticks 20632000 # Number of ticks simulated
-final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 21078000 # Number of ticks simulated
+final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1782 # Simulator instruction rate (inst/s)
-host_op_rate 1782 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5769044 # Simulator tick rate (ticks/s)
-host_mem_usage 227476 # Number of bytes of host memory used
-host_seconds 3.58 # Real time elapsed on the host
+host_inst_rate 72140 # Simulator instruction rate (inst/s)
+host_op_rate 72127 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 238549554 # Simulator tick rate (ticks/s)
+host_mem_usage 265696 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory
system.physmem.bytes_read::total 31168 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
system.physmem.num_reads::total 487 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 488 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 31168 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 20599000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 488 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
+system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 488 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 69 # Per bank write bursts
+system.physmem.perBankRdBursts::1 34 # Per bank write bursts
+system.physmem.perBankRdBursts::2 32 # Per bank write bursts
+system.physmem.perBankRdBursts::3 47 # Per bank write bursts
+system.physmem.perBankRdBursts::4 43 # Per bank write bursts
+system.physmem.perBankRdBursts::5 21 # Per bank write bursts
+system.physmem.perBankRdBursts::6 1 # Per bank write bursts
+system.physmem.perBankRdBursts::7 3 # Per bank write bursts
+system.physmem.perBankRdBursts::8 0 # Per bank write bursts
+system.physmem.perBankRdBursts::9 1 # Per bank write bursts
+system.physmem.perBankRdBursts::10 23 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24 # Per bank write bursts
+system.physmem.perBankRdBursts::12 14 # Per bank write bursts
+system.physmem.perBankRdBursts::13 119 # Per bank write bursts
+system.physmem.perBankRdBursts::14 45 # Per bank write bursts
+system.physmem.perBankRdBursts::15 12 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 21045000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 488 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
-system.physmem.totQLat 2633750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests
-system.physmem.totBusLat 2440000 # Total cycles spent in databus access
-system.physmem.totBankLat 7562500 # Total cycles spent in bank access
-system.physmem.avgQLat 5397.03 # Average queueing delay per request
-system.physmem.avgBankLat 15496.93 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25893.95 # Average memory access latency
-system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.80 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.61 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 419 # Number of row buffer hits during reads
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation
+system.physmem.totQLat 3243750 # Total ticks spent queuing
+system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 7645000 # Total ticks spent accessing banks
+system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 11.58 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 394 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 42211.07 # Average gap between requests
-system.membus.throughput 1510663048 # Throughput (bytes/s)
+system.physmem.avgGap 43125.00 # Average gap between requests
+system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput 1478698169 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 415 # Transaction distribution
system.membus.trans_dist::ReadResp 414 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 975 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 31168 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
-system.cpu.branchPred.lookups 2906 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 759 # Number of BTB hits
+system.membus.respLayer1.utilization 21.6 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 2894 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2209 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 756 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 34.223631 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2097 # DTB read hits
+system.cpu.dtb.read_hits 2078 # DTB read hits
system.cpu.dtb.read_misses 47 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2144 # DTB read accesses
-system.cpu.dtb.write_hits 1063 # DTB write hits
+system.cpu.dtb.read_accesses 2125 # DTB read accesses
+system.cpu.dtb.write_hits 1062 # DTB write hits
system.cpu.dtb.write_misses 31 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1094 # DTB write accesses
-system.cpu.dtb.data_hits 3160 # DTB hits
+system.cpu.dtb.write_accesses 1093 # DTB write accesses
+system.cpu.dtb.data_hits 3140 # DTB hits
system.cpu.dtb.data_misses 78 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3238 # DTB accesses
-system.cpu.itb.fetch_hits 2393 # ITB hits
+system.cpu.dtb.data_accesses 3218 # DTB accesses
+system.cpu.itb.fetch_hits 2388 # ITB hits
system.cpu.itb.fetch_misses 39 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2432 # ITB accesses
+system.cpu.itb.fetch_accesses 2427 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 41265 # number of cpu cycles simulated
+system.cpu.numCycles 42157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2793 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2770 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2621 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename
+system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2628 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
+system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10814 # Type of FU issued
-system.cpu.iq.rate 0.262062 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 111 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10780 # Type of FU issued
+system.cpu.iq.rate 0.255711 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 112 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 89 # number of nop insts executed
-system.cpu.iew.exec_refs 3251 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1595 # Number of branches executed
-system.cpu.iew.exec_stores 1096 # Number of stores executed
-system.cpu.iew.exec_rate 0.245147 # Inst execution rate
-system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9641 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5053 # num instructions producing a value
-system.cpu.iew.wb_consumers 6805 # num instructions consuming a value
+system.cpu.iew.exec_refs 3231 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1589 # Number of branches executed
+system.cpu.iew.exec_stores 1095 # Number of stores executed
+system.cpu.iew.exec_rate 0.238916 # Inst execution rate
+system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9612 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5080 # num instructions producing a value
+system.cpu.iew.wb_consumers 6838 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 26491 # The number of ROB reads
-system.cpu.rob.rob_writes 27437 # The number of ROB writes
-system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 26334 # The number of ROB reads
+system.cpu.rob.rob_writes 27415 # The number of ROB writes
+system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
-system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12831 # number of integer regfile reads
-system.cpu.int_regfile_writes 7294 # number of integer regfile writes
+system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12785 # number of integer regfile reads
+system.cpu.int_regfile_writes 7268 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use
-system.cpu.icache.total_refs 1903 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 159.617277 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.077938 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.077938 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1903 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1903 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1903 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1903 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1903 # number of overall hits
-system.cpu.icache.overall_hits::total 1903 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses
-system.cpu.icache.overall_misses::total 490 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 30064500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 30064500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 30064500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 30064500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 30064500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 30064500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2393 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2393 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2393 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2393 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2393 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2393 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204764 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.204764 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.204764 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.204764 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.204764 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.204764 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61356.122449 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61356.122449 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61356.122449 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61356.122449 # average overall miss latency
+system.cpu.icache.tags.replacements 0 # number of replacements
+system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 5090 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits
+system.cpu.icache.overall_hits::total 1899 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses
+system.cpu.icache.overall_misses::total 489 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles
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system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
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-system.cpu.dcache.overall_hits::total 2246 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 529 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11698500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11698500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723478 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 21723478 # number of WriteReq miss cycles
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-system.cpu.dcache.overall_miss_latency::cpu.data 33421978 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33421978 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1910 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1910 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2775 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 2775 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089005 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.089005 # miss rate for ReadReq accesses
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+system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63179.542533 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63179.542533 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 1568 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.515152 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff