---------- Begin Simulation Statistics ----------
-sim_seconds 0.000224 # Number of seconds simulated
-sim_ticks 223694 # Number of ticks simulated
-final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000109 # Number of seconds simulated
+sim_ticks 108694 # Number of ticks simulated
+final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 19611 # Simulator instruction rate (inst/s)
-host_tick_rate 684980 # Simulator tick rate (ticks/s)
-host_mem_usage 219636 # Number of bytes of host memory used
-host_seconds 0.33 # Real time elapsed on the host
-sim_insts 6404 # Number of instructions simulated
-system.physmem.bytes_read 34460 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 6696 # Number of bytes written to this memory
-system.physmem.num_reads 7599 # Number of read requests responded to by this memory
-system.physmem.num_writes 865 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 154049729 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 114692392 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 29933749 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 183983477 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 21195 # Simulator instruction rate (inst/s)
+host_op_rate 21193 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 360456 # Simulator tick rate (ticks/s)
+host_mem_usage 391840 # Number of bytes of host memory used
+host_seconds 0.30 # Real time elapsed on the host
+sim_insts 6390 # Number of instructions simulated
+sim_ops 6390 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75648 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 75648 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 695972179 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 695972179 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 114228936 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 114228936 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 810201115 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 810201115 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1182 # Number of read requests accepted
+system.mem_ctrls.writeReqs 194 # Number of write requests accepted
+system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 64448 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 82 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 66 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
+system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
+system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
+system.mem_ctrls.totGap 108642 # Total gap between requests
+system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1182 # Read request sizes (log2)
+system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 1007 # What read queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 335.524752 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 204.886741 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 324.305016 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 65 32.18% 32.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 55.45% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 21 10.40% 65.84% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 14 6.93% 72.77% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 12 5.94% 78.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 11 5.45% 84.16% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 6 2.97% 87.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 89.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 21 10.40% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 141.200000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 107.481731 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 78.180560 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 6988 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 26121 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5035 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst
+system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
+system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 592.93 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 50.05 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 695.97 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 114.23 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.mem_ctrls.busUtil 5.02 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 21.56 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 77 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 80.14 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 68.75 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 78.95 # Average gap between requests
+system.mem_ctrls.pageHitRate 79.00 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 62170812 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 6351000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 81199236 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 800.165908 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 15769 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 87863 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 67286448 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 1863600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 84579504 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 833.476261 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 2630 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 95482 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2050 # DTB hits
+system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2060 # DTB accesses
-system.cpu.itb.fetch_hits 6415 # ITB hits
+system.cpu.dtb.data_accesses 2058 # DTB accesses
+system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6432 # ITB accesses
+system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 223694 # number of cpu cycles simulated
+system.cpu.numCycles 108694 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
+system.cpu.committedInsts 6390 # Number of instructions committed
+system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6331 # number of integer instructions
+system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2060 # number of memory refs
-system.cpu.num_load_insts 1192 # Number of load instructions
+system.cpu.num_mem_refs 2058 # number of memory refs
+system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 223694 # Number of busy cycles
+system.cpu.num_busy_cycles 108694 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
+system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
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+system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
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+system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
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+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
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+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
+system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 6400 # Class of executed instruction
+system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size 1
+system.ruby.outstanding_req_hist::max_bucket 9
+system.ruby.outstanding_req_hist::samples 8449
+system.ruby.outstanding_req_hist::mean 1
+system.ruby.outstanding_req_hist::gmean 1
+system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 8449
+system.ruby.latency_hist::bucket_size 64
+system.ruby.latency_hist::max_bucket 639
+system.ruby.latency_hist::samples 8448
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+system.ruby.latency_hist::gmean 1.974485
+system.ruby.latency_hist::stdev 27.814086
+system.ruby.latency_hist | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 8448
+system.ruby.hit_latency_hist::bucket_size 1
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+system.ruby.hit_latency_hist::samples 7027
+system.ruby.hit_latency_hist::mean 1
+system.ruby.hit_latency_hist::gmean 1
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 7027
+system.ruby.miss_latency_hist::bucket_size 64
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+system.ruby.miss_latency_hist::gmean 57.082853
+system.ruby.miss_latency_hist::stdev 33.588801
+system.ruby.miss_latency_hist | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 1421
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+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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+system.ruby.LD.latency_hist::bucket_size 64
+system.ruby.LD.latency_hist::max_bucket 639
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+system.ruby.LD.latency_hist::gmean 5.733715
+system.ruby.LD.latency_hist::stdev 35.817674
+system.ruby.LD.latency_hist | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist::total 1183
+system.ruby.LD.hit_latency_hist::bucket_size 1
+system.ruby.LD.hit_latency_hist::max_bucket 9
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+system.ruby.LD.hit_latency_hist::mean 1
+system.ruby.LD.hit_latency_hist::gmean 1
+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist::total 658
+system.ruby.LD.miss_latency_hist::bucket_size 64
+system.ruby.LD.miss_latency_hist::max_bucket 639
+system.ruby.LD.miss_latency_hist::samples 525
+system.ruby.LD.miss_latency_hist::mean 60.184762
+system.ruby.LD.miss_latency_hist::gmean 51.169278
+system.ruby.LD.miss_latency_hist::stdev 30.689440
+system.ruby.LD.miss_latency_hist | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist::total 525
+system.ruby.ST.latency_hist::bucket_size 64
+system.ruby.ST.latency_hist::max_bucket 639
+system.ruby.ST.latency_hist::samples 865
+system.ruby.ST.latency_hist::mean 17.593064
+system.ruby.ST.latency_hist::gmean 3.080574
+system.ruby.ST.latency_hist::stdev 34.156278
+system.ruby.ST.latency_hist | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist::total 865
+system.ruby.ST.hit_latency_hist::bucket_size 1
+system.ruby.ST.hit_latency_hist::max_bucket 9
+system.ruby.ST.hit_latency_hist::samples 615
+system.ruby.ST.hit_latency_hist::mean 1
+system.ruby.ST.hit_latency_hist::gmean 1
+system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist::total 615
+system.ruby.ST.miss_latency_hist::bucket_size 64
+system.ruby.ST.miss_latency_hist::max_bucket 639
+system.ruby.ST.miss_latency_hist::samples 250
+system.ruby.ST.miss_latency_hist::mean 58.412000
+system.ruby.ST.miss_latency_hist::gmean 49.053018
+system.ruby.ST.miss_latency_hist::stdev 41.173185
+system.ruby.ST.miss_latency_hist | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 250
+system.ruby.IFETCH.latency_hist::bucket_size 32
+system.ruby.IFETCH.latency_hist::max_bucket 319
+system.ruby.IFETCH.latency_hist::samples 6400
+system.ruby.IFETCH.latency_hist::mean 8.245781
+system.ruby.IFETCH.latency_hist::gmean 1.526741
+system.ruby.IFETCH.latency_hist::stdev 23.776931
+system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00%
+system.ruby.IFETCH.latency_hist::total 6400
+system.ruby.IFETCH.hit_latency_hist::bucket_size 1
+system.ruby.IFETCH.hit_latency_hist::max_bucket 9
+system.ruby.IFETCH.hit_latency_hist::samples 5754
+system.ruby.IFETCH.hit_latency_hist::mean 1
+system.ruby.IFETCH.hit_latency_hist::gmean 1
+system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist::total 5754
+system.ruby.IFETCH.miss_latency_hist::bucket_size 32
+system.ruby.IFETCH.miss_latency_hist::max_bucket 319
+system.ruby.IFETCH.miss_latency_hist::samples 646
+system.ruby.IFETCH.miss_latency_hist::mean 72.784830
+system.ruby.IFETCH.miss_latency_hist::gmean 66.158480
+system.ruby.IFETCH.miss_latency_hist::stdev 31.122591
+system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 646
+system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 984 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 194 0.00% 0.00%
+system.ruby.Directory_Controller.Unblock 466 0.00% 0.00%
+system.ruby.Directory_Controller.Last_Unblock 517 0.00% 0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00%
+system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00%
+system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock 517 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 1125 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 1308 0.00% 0.00%
+system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 525 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Load 299 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Ifetch 5754 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 1059 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Load 39 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout 45 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Load 228 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 242 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 354 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement 14 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 1125 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1013 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 1171 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 1059 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 1182 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1013 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 1171 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 1193 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 984 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1013 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 906 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1013 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 984 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 984 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 198 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00%
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff