---------- Begin Simulation Statistics ----------
-sim_seconds 0.000007 # Number of seconds simulated
-sim_ticks 6833000 # Number of ticks simulated
-final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 12363500 # Number of ticks simulated
+final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46364 # Simulator instruction rate (inst/s)
-host_tick_rate 132671945 # Simulator tick rate (ticks/s)
-host_mem_usage 207164 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 12168 # Simulator instruction rate (inst/s)
+host_op_rate 12166 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63007670 # Simulator tick rate (ticks/s)
+host_mem_usage 231556 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
-system.physmem.bytes_read 17280 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 270 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s)
+sim_ops 2387 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
+system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 968010677 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 440004853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1408015530 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 968010677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 968010677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 968010677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 440004853 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1408015530 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 272 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 17408 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 17408 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 0 # Per bank write bursts
+system.physmem.perBankRdBursts::1 1 # Per bank write bursts
+system.physmem.perBankRdBursts::2 2 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18 # Per bank write bursts
+system.physmem.perBankRdBursts::5 0 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24 # Per bank write bursts
+system.physmem.perBankRdBursts::7 37 # Per bank write bursts
+system.physmem.perBankRdBursts::8 60 # Per bank write bursts
+system.physmem.perBankRdBursts::9 2 # Per bank write bursts
+system.physmem.perBankRdBursts::10 15 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9 # Per bank write bursts
+system.physmem.perBankRdBursts::12 17 # Per bank write bursts
+system.physmem.perBankRdBursts::13 50 # Per bank write bursts
+system.physmem.perBankRdBursts::14 12 # Per bank write bursts
+system.physmem.perBankRdBursts::15 1 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 12267000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 272 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 152 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
+system.physmem.totQLat 1685750 # Total ticks spent queuing
+system.physmem.totMemAccLat 6785750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 6197.61 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 24947.61 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1408.02 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1408.02 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 11.00 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.00 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 226 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 45099.26 # Average gap between requests
+system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ)
+system.physmem_0.averagePower 833.570297 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ)
+system.physmem_1.averagePower 866.151313 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.cpu.branchPred.lookups 890 # Number of BP lookups
+system.cpu.branchPred.condPredicted 443 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 195 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 616 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 164 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 26.623377 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 186 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 679 # DTB read hits
-system.cpu.dtb.read_misses 26 # DTB read misses
+system.cpu.dtb.read_hits 719 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 705 # DTB read accesses
-system.cpu.dtb.write_hits 356 # DTB write hits
-system.cpu.dtb.write_misses 18 # DTB write misses
+system.cpu.dtb.read_accesses 729 # DTB read accesses
+system.cpu.dtb.write_hits 347 # DTB write hits
+system.cpu.dtb.write_misses 16 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 374 # DTB write accesses
-system.cpu.dtb.data_hits 1035 # DTB hits
-system.cpu.dtb.data_misses 44 # DTB misses
+system.cpu.dtb.write_accesses 363 # DTB write accesses
+system.cpu.dtb.data_hits 1066 # DTB hits
+system.cpu.dtb.data_misses 26 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1079 # DTB accesses
-system.cpu.itb.fetch_hits 941 # ITB hits
-system.cpu.itb.fetch_misses 30 # ITB misses
+system.cpu.dtb.data_accesses 1092 # DTB accesses
+system.cpu.itb.fetch_hits 802 # ITB hits
+system.cpu.itb.fetch_misses 35 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 971 # ITB accesses
+system.cpu.itb.fetch_accesses 837 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 13667 # number of cpu cycles simulated
+system.cpu.numCycles 24728 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 1038 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 941 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 4265 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 5512 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 890 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 350 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1015 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 436 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1206 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 802 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 6733 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.818654 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.224131 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 5799 86.13% 86.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 30 0.45% 86.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 91 1.35% 87.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 76 1.13% 89.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 118 1.75% 90.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 72 1.07% 91.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40 0.59% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 56 0.83% 93.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 451 6.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1081 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 995 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename
-system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 6733 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.035992 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.222905 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5190 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 505 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 865 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 28 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 145 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 132 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 4839 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 145 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5257 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 824 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 7 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 4680 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenamedOperands 3347 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5277 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5270 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 1579 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 52 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 418 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 4078 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 3608 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 32 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1696 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 859 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 6733 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.535868 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.279819 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5352 79.49% 79.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 449 6.67% 86.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 318 4.72% 90.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 240 3.56% 94.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 185 2.75% 97.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 110 1.63% 98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 49 0.73% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 21 0.31% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 6733 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 8.70% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 39 56.52% 65.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 24 34.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2482 68.79% 68.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.03% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 757 20.98% 89.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 368 10.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 3881 # Type of FU issued
-system.cpu.iq.rate 0.283969 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 41 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 3608 # Type of FU issued
+system.cpu.iq.rate 0.145907 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 69 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019124 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 14037 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 5777 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3273 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 3670 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 380 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 124 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 145 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 4365 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 29 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 418 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 20 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 120 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 140 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 3509 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 730 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 99 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 338 # number of nop insts executed
-system.cpu.iew.exec_refs 1080 # number of memory reference insts executed
-system.cpu.iew.exec_branches 629 # Number of branches executed
-system.cpu.iew.exec_stores 374 # Number of stores executed
-system.cpu.iew.exec_rate 0.274310 # Inst execution rate
-system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3579 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1702 # num instructions producing a value
-system.cpu.iew.wb_consumers 2165 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 281 # number of nop insts executed
+system.cpu.iew.exec_refs 1093 # number of memory reference insts executed
+system.cpu.iew.exec_branches 570 # Number of branches executed
+system.cpu.iew.exec_stores 363 # Number of stores executed
+system.cpu.iew.exec_rate 0.141904 # Inst execution rate
+system.cpu.iew.wb_sent 3329 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3279 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1560 # num instructions producing a value
+system.cpu.iew.wb_consumers 1998 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.132603 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.780781 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 1787 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 122 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 6402 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.402374 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.273029 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 5545 86.61% 86.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 194 3.03% 89.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 304 4.75% 94.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 116 1.81% 96.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 62 0.97% 97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 60 0.94% 98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 35 0.55% 98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 20 0.31% 98.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 66 1.03% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle
-system.cpu.commit.count 2576 # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 6402 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 2576 # Number of instructions committed
+system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 10645 # The number of ROB reads
-system.cpu.rob.rob_writes 10410 # The number of ROB writes
-system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
+system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 10452 # The number of ROB reads
+system.cpu.rob.rob_writes 9060 # The number of ROB writes
+system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 17995 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
-system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4520 # number of integer regfile reads
-system.cpu.int_regfile_writes 2768 # number of integer regfile writes
+system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 10.359447 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 10.359447 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.096530 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.096530 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 4249 # number of integer regfile reads
+system.cpu.int_regfile_writes 2511 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use
-system.cpu.icache.total_refs 700 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits
-system.cpu.icache.demand_hits 700 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 700 # number of overall hits
-system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
-system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 241 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use
-system.cpu.dcache.total_refs 765 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits
-system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 765 # number of overall hits
-system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses
-system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 173 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 45.334739 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 716 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.423529 # Average number of references to valid blocks.
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-system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 187 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
+system.cpu.l2cache.overall_misses::total 272 # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13898000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 13898000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 13898000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6532000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20430000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 13898000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6532000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20430000 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 187 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74320.855615 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74320.855615 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77352.459016 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77352.459016 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75110.294118 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75110.294118 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 7661500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 8417500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 8417500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12028000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12028000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12028000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5682000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17710000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12028000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5682000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17710000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64320.855615 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64320.855615 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67352.459016 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67352.459016 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.trans_dist::ReadResp 248 # Transaction distribution
+system.membus.trans_dist::ReadExReq 24 # Transaction distribution
+system.membus.trans_dist::ReadExResp 24 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 272 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 272 # Request fanout histogram
+system.membus.reqLayer0.occupancy 335500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1441000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff