---------- Begin Simulation Statistics ----------
-sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21759500 # Number of ticks simulated
-final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000024 # Number of seconds simulated
+sim_ticks 24405000 # Number of ticks simulated
+final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 43168 # Simulator instruction rate (inst/s)
-host_op_rate 43158 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 182102261 # Simulator tick rate (ticks/s)
-host_mem_usage 228268 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
-sim_insts 5156 # Number of instructions simulated
-sim_ops 5156 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 478 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 478 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30592 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 21680500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 478 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+host_inst_rate 119579 # Simulator instruction rate (inst/s)
+host_op_rate 119550 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 583509526 # Simulator tick rate (ticks/s)
+host_mem_usage 251420 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+sim_insts 4999 # Number of instructions simulated
+sim_ops 4999 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 862774022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 367137882 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1229911903 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 862774022 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 862774022 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 862774022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 367137882 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1229911903 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 469 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 29 # Per bank write bursts
+system.physmem.perBankRdBursts::1 0 # Per bank write bursts
+system.physmem.perBankRdBursts::2 1 # Per bank write bursts
+system.physmem.perBankRdBursts::3 0 # Per bank write bursts
+system.physmem.perBankRdBursts::4 7 # Per bank write bursts
+system.physmem.perBankRdBursts::5 3 # Per bank write bursts
+system.physmem.perBankRdBursts::6 13 # Per bank write bursts
+system.physmem.perBankRdBursts::7 53 # Per bank write bursts
+system.physmem.perBankRdBursts::8 59 # Per bank write bursts
+system.physmem.perBankRdBursts::9 76 # Per bank write bursts
+system.physmem.perBankRdBursts::10 43 # Per bank write bursts
+system.physmem.perBankRdBursts::11 21 # Per bank write bursts
+system.physmem.perBankRdBursts::12 51 # Per bank write bursts
+system.physmem.perBankRdBursts::13 29 # Per bank write bursts
+system.physmem.perBankRdBursts::14 77 # Per bank write bursts
+system.physmem.perBankRdBursts::15 7 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 24305500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 469 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation
-system.physmem.totQLat 2435500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests
-system.physmem.totBusLat 2390000 # Total cycles spent in databus access
-system.physmem.totBankLat 8676250 # Total cycles spent in bank access
-system.physmem.avgQLat 5095.19 # Average queueing delay per request
-system.physmem.avgBankLat 18151.15 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28246.34 # Average memory access latency
-system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 10.98 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.62 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 375 # Number of row buffer hits during reads
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 114 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 261.614035 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.762153 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 255.654479 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 36 31.58% 31.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 34 29.82% 61.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation
+system.physmem.totQLat 7589250 # Total ticks spent queuing
+system.physmem.totMemAccLat 16383000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 16181.77 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 34931.77 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 9.61 # Data bus utilization in percentage
+system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 352 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45356.69 # Average gap between requests
-system.membus.throughput 1405914658 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 427 # Transaction distribution
-system.membus.trans_dist::ReadResp 427 # Transaction distribution
-system.membus.trans_dist::ReadExReq 51 # Transaction distribution
-system.membus.trans_dist::ReadExResp 51 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 956 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 30592 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 20.6 # Layer utilization (%)
-system.cpu.branchPred.lookups 2196 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 505 # Number of BTB hits
+system.physmem.avgGap 51824.09 # Average gap between requests
+system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1603980 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 8337960 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ)
+system.physmem_0.averagePower 566.830977 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states
+system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 4208310 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 89280 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 6602310 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 178560 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 16490760 # Total energy per rank (pJ)
+system.physmem_1.averagePower 675.712354 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 14474500 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 2177 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1448 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 422 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 589 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 33.108488 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 268 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 95 # Number of mispredicted indirect branches.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 43520 # number of cpu cycles simulated
+system.cpu.workload.numSyscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 48811 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 9085 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12947 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2177 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 842 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 5440 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing
+system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2046 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 261 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 15162 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.853911 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.140587 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11809 77.89% 77.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1506 9.93% 87.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 111 0.73% 88.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 164 1.08% 89.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 279 1.84% 91.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 101 0.67% 92.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 136 0.90% 93.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 158 1.04% 94.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 898 5.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3054 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2924 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.fetch.rateDist::total 15162 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.044601 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.265248 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8416 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3447 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2766 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 141 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 392 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 589 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 11962 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 392 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8568 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 617 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2736 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11523 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 6897 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 13509 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13276 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 3605 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2464 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 8995 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8108 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4006 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1995 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 15162 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.534758 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.264874 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11839 78.08% 78.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1338 8.82% 86.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 727 4.79% 91.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 451 2.97% 94.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 343 2.26% 96.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 283 1.87% 98.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 110 0.73% 99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 52 0.34% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 15162 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4767 58.79% 58.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2271 28.01% 86.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1063 13.11% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8313 # Type of FU issued
-system.cpu.iq.rate 0.191016 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 159 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8108 # Type of FU issued
+system.cpu.iq.rate 0.166110 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.022200 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31574 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 13019 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7329 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8286 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1329 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 392 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 487 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10600 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2464 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 335 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 436 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7776 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2123 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 332 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1529 # number of nop insts executed
-system.cpu.iew.exec_refs 3196 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1356 # Number of branches executed
-system.cpu.iew.exec_stores 1078 # Number of stores executed
-system.cpu.iew.exec_rate 0.182353 # Inst execution rate
-system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7469 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2922 # num instructions producing a value
-system.cpu.iew.wb_consumers 4200 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 1594 # number of nop insts executed
+system.cpu.iew.exec_refs 3172 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1361 # Number of branches executed
+system.cpu.iew.exec_stores 1049 # Number of stores executed
+system.cpu.iew.exec_rate 0.159308 # Inst execution rate
+system.cpu.iew.wb_sent 7424 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7331 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2863 # num instructions producing a value
+system.cpu.iew.wb_consumers 4269 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.150192 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.670649 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 4961 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 14286 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.394792 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.199270 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 12095 84.66% 84.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 883 6.18% 90.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 522 3.65% 94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 63 0.44% 99.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 41 0.29% 99.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 5813 # Number of instructions committed
-system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 14286 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 5640 # Number of instructions committed
+system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 2088 # Number of memory references committed
-system.cpu.commit.loads 1163 # Number of loads committed
+system.cpu.commit.refs 2036 # Number of memory references committed
+system.cpu.commit.loads 1135 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 915 # Number of branches committed
+system.cpu.commit.branches 886 # Number of branches committed
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
-system.cpu.commit.function_calls 87 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 24277 # The number of ROB reads
-system.cpu.rob.rob_writes 22442 # The number of ROB writes
-system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 5156 # Number of Instructions Simulated
-system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
-system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10757 # number of integer regfile reads
-system.cpu.int_regfile_writes 5239 # number of integer regfile writes
+system.cpu.commit.int_insts 4955 # Number of committed integer instructions.
+system.cpu.commit.function_calls 85 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
+system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 24772 # The number of ROB reads
+system.cpu.rob.rob_writes 22085 # The number of ROB writes
+system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 33649 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 4999 # Number of Instructions Simulated
+system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10585 # number of integer regfile reads
+system.cpu.int_regfile_writes 5135 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
-system.cpu.misc_regfile_reads 148 # number of misc regfile reads
-system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57746.279762 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65483.516484 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59395.199063 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63107.843137 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63107.843137 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 91.370944 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2400 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.901408 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 91.370944 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.022307 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.022307 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits
-system.cpu.dcache.overall_hits::total 2400 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
-system.cpu.dcache.overall_misses::total 511 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 10242000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 22669999 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 22669999 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 32911999 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 32911999 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 32911999 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 32911999 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1986 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2911 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2911 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2911 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2911 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075025 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.075025 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.175541 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.175541 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.175541 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.175541 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68738.255034 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68738.255034 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62624.306630 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62624.306630 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64407.043053 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73869.300912 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73869.300912 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 419 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50 # Transaction distribution
+system.membus.trans_dist::ReadExResp 50 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 469 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 469 # Request fanout histogram
+system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 10.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff