tests: Update RISC-V hello test and stats

[gem5.git] / tests / quick / se / 00.hello / ref / riscv / linux / simple-timing / simout

diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
index b345196147d595a99ebe4a4ca9623813ac500cb9..385bb2b92cb43c4c1dc0063495048cce98071016 100755 (executable)
--- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout
-Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr
+Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simout
+Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:29
-gem5 executing on zizzer, pid 34059
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
+gem5 compiled May 31 2017 18:33:59
+gem5 started May 31 2017 18:34:14
+gem5 executing on boldrock, pid 15728
+command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
 
 Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 11602500 because target called exit()
+Exiting @ tick 34045500 because exiting with last active thread context