---------- Begin Simulation Statistics ----------
-sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 11602500 # Number of ticks simulated
-final_tick 11602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 36172 # Simulator instruction rate (inst/s)
-host_op_rate 36155 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 264212858 # Simulator tick rate (ticks/s)
-host_mem_usage 230876 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-sim_insts 1587 # Number of instructions simulated
-sim_ops 1587 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9728 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 7808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7808 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 30 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 152 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 672958414 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 165481577 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 838439991 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 672958414 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 672958414 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 672958414 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 165481577 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 838439991 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 9 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 23205 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1587 # Number of instructions committed
-system.cpu.committedOps 1587 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 142 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1588 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 2062 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1077 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 569 # number of memory refs
-system.cpu.num_load_insts 289 # Number of load instructions
-system.cpu.num_store_insts 280 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 23205 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 373 # Number of branches fetched
-system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction
-system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction
-system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction
-system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1597 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 22.779229 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 537 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 17.322581 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 22.779229 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.005561 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.005561 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1167 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1167 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 276 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 276 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 261 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 261 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 537 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 537 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 537 # number of overall hits
-system.cpu.dcache.overall_hits::total 537 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 18 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 18 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 31 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 31 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 31 # number of overall misses
-system.cpu.dcache.overall_misses::total 31 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 770000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 770000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1134000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1134000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1904000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1904000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1904000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1904000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 289 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 289 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 568 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 568 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 568 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 568 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.044983 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.044983 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.064516 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.064516 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.054577 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.054577 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.054577 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.054577 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59230.769231 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59230.769231 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61419.354839 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61419.354839 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 13 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 13 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 31 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 31 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 31 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 31 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 757000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 757000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1116000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1116000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1873000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 1873000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1873000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 1873000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044983 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044983 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.054577 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.054577 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58230.769231 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58230.769231 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 56.912998 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1476 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 122 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 12.098361 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 56.912998 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.027790 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.027790 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 122 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.059570 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 3318 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 3318 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 1476 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1476 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1476 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1476 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1476 # number of overall hits
-system.cpu.icache.overall_hits::total 1476 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 122 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 122 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 122 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 122 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 122 # number of overall misses
-system.cpu.icache.overall_misses::total 122 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 7686500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 7686500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 7686500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 7686500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 7686500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 7686500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1598 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1598 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1598 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1598 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1598 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076345 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.076345 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.076345 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.076345 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.076345 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.076345 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63004.098361 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 63004.098361 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 63004.098361 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 63004.098361 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 122 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 122 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7564500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 7564500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7564500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 7564500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7564500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 7564500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076345 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.076345 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.076345 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62004.098361 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62004.098361 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 78.991344 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 152 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.006579 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 57.023406 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21.967939 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001740 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.000670 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.002411 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 152 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.004639 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 1376 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 1376 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 122 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 122 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 12 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 122 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 30 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 152 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 122 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 30 # number of overall misses
-system.cpu.l2cache.overall_misses::total 152 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1089000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1089000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7381500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 7381500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 726000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 726000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 7381500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 1815000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 9196500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 7381500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 1815000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 9196500 # number of overall miss cycles
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-system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 122 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 122 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 13 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 13 # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.data 31 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 153 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 122 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 31 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 153 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.923077 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.923077 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.967742 # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data 0.967742 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.993464 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.098361 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.098361 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 60503.289474 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 60503.289474 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 122 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 122 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 30 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 152 # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.data 30 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 152 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 909000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 909000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6161500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6161500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 606000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 606000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6161500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1515000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 7676500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6161500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1515000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 7676500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.923077 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.923077 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.993464 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.993464 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.098361 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.098361 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 153 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 135 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 122 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 244 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 306 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7808 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1984 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 9792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 153 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.006536 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.080845 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 152 99.35% 99.35% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1 0.65% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 153 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 76500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 183000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 46500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 152 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 134 # Transaction distribution
-system.membus.trans_dist::ReadExReq 18 # Transaction distribution
-system.membus.trans_dist::ReadExResp 18 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 134 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 304 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 304 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 9728 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 9728 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 152 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 152 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 152 # Request fanout histogram
-system.membus.reqLayer0.occupancy 152500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 760000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 6.6 # Layer utilization (%)
+sim_seconds 0.000034
+sim_ticks 34045500
+final_tick 34045500
+sim_freq 1000000000000
+host_inst_rate 83295
+host_op_rate 83403
+host_tick_rate 510821707
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+system.cpu.num_int_register_writes 3562
+system.cpu.num_fp_register_reads 12
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+system.cpu.num_load_insts 1101
+system.cpu.num_store_insts 1097
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 68091
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 1205
+system.cpu.op_class::No_OpClass 10 0.18% 0.18%
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+system.cpu.toL2Bus.snoop_filter.tot_requests 424
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
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+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34045500
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+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558
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+system.cpu.toL2Bus.pkt_size::total 27136
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 424
+system.cpu.toL2Bus.snoop_fanout::mean 0
+system.cpu.toL2Bus.snoop_fanout::stdev 0
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 424 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 0
+system.cpu.toL2Bus.snoop_fanout::total 424
+system.cpu.toL2Bus.reqLayer0.occupancy 212000
+system.cpu.toL2Bus.reqLayer0.utilization 0.6
+system.cpu.toL2Bus.respLayer0.occupancy 418500
+system.cpu.toL2Bus.respLayer0.utilization 1.2
+system.cpu.toL2Bus.respLayer1.occupancy 217500
+system.cpu.toL2Bus.respLayer1.utilization 0.6
+system.membus.snoop_filter.tot_requests 424
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+system.membus.pwrStateResidencyTicks::UNDEFINED 34045500
+system.membus.trans_dist::ReadResp 342
+system.membus.trans_dist::ReadExReq 82
+system.membus.trans_dist::ReadExResp 82
+system.membus.trans_dist::ReadSharedReq 342
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+system.membus.pkt_count::total 848
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+system.membus.pkt_size::total 27136
+system.membus.snoops 0
+system.membus.snoopTraffic 0
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+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 424 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 424
+system.membus.reqLayer0.occupancy 424500
+system.membus.reqLayer0.utilization 1.2
+system.membus.respLayer1.occupancy 2120000
+system.membus.respLayer1.utilization 6.2
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff