---------- Begin Simulation Statistics ----------
-sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29726000 # Number of ticks simulated
-final_tick 29726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000031 # Number of seconds simulated
+sim_ticks 30886500 # Number of ticks simulated
+final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107097 # Simulator instruction rate (inst/s)
-host_op_rate 193883 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 587308683 # Simulator tick rate (ticks/s)
-host_mem_usage 226300 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-sim_insts 5417 # Number of instructions simulated
-sim_ops 9810 # Number of ops (including micro ops) simulated
+host_inst_rate 73831 # Simulator instruction rate (inst/s)
+host_op_rate 133710 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 423540181 # Simulator tick rate (ticks/s)
+host_mem_usage 246764 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+sim_insts 5381 # Number of instructions simulated
+sim_ops 9748 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 488730404 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 288501648 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 777232053 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 488730404 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 488730404 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 488730404 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 288501648 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 777232053 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 59452 # number of cpu cycles simulated
+system.cpu.numCycles 61773 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5417 # Number of instructions committed
-system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
+system.cpu.committedInsts 5381 # Number of instructions committed
+system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
-system.cpu.num_int_insts 9715 # number of integer instructions
+system.cpu.num_func_calls 209 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
+system.cpu.num_int_insts 9654 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 29934 # number of times the integer registers were read
-system.cpu.num_int_register_writes 14707 # number of times the integer registers were written
+system.cpu.num_int_register_reads 18335 # number of times the integer registers were read
+system.cpu.num_int_register_writes 7527 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1990 # number of memory refs
-system.cpu.num_load_insts 1056 # Number of load instructions
-system.cpu.num_store_insts 934 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 59452 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 105.590396 # Cycle average of tags in use
-system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 105.590396 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.051558 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.051558 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits
-system.cpu.icache.overall_hits::total 6683 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
-system.cpu.icache.overall_misses::total 228 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.032991 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.032991 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.032991 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032991 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.032991 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.032991 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 80.767478 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 80.767478 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.019719 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.019719 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits
-system.cpu.dcache.overall_hits::total 1856 # number of overall hits
+system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written
+system.cpu.num_mem_refs 1988 # number of memory refs
+system.cpu.num_load_insts 1053 # Number of load instructions
+system.cpu.num_store_insts 935 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 1208 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
+system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction
+system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction
+system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction
+system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction
+system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 9748 # Class of executed instruction
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 1854 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.dcache.overall_misses::total 134 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.052083 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067337 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067337 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.trans_dist::ReadResp 282 # Transaction distribution
+system.membus.trans_dist::ReadExReq 79 # Transaction distribution
+system.membus.trans_dist::ReadExResp 79 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 361 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 361 # Request fanout histogram
+system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff