---------- Begin Simulation Statistics ----------
-sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 28358500 # Number of ticks simulated
-final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000031 # Number of seconds simulated
+sim_ticks 30886500 # Number of ticks simulated
+final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97635 # Simulator instruction rate (inst/s)
-host_op_rate 176805 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 514168344 # Simulator tick rate (ticks/s)
-host_mem_usage 251928 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 73831 # Simulator instruction rate (inst/s)
+host_op_rate 133710 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 423540181 # Simulator tick rate (ticks/s)
+host_mem_usage 246764 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 56717 # number of cpu cycles simulated
+system.cpu.numCycles 61773 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1208 # Number of branches fetched
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.dcache.overall_misses::total 134 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses
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system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses
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+system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.l2cache.overall_misses::total 361 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 282 # Transaction distribution
system.membus.trans_dist::ReadResp 282 # Transaction distribution
system.membus.trans_dist::ReadExReq 79 # Transaction distribution
system.membus.trans_dist::ReadExResp 79 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 361 # Request fanout histogram
system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
+system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff