---------- Begin Simulation Statistics ----------
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13973500 # Number of ticks simulated
-final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000024 # Number of seconds simulated
+sim_ticks 24229500 # Number of ticks simulated
+final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 43715 # Simulator instruction rate (inst/s)
-host_op_rate 43711 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47815570 # Simulator tick rate (ticks/s)
-host_mem_usage 215652 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
-sim_insts 12773 # Number of instructions simulated
-sim_ops 12773 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 62784 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 981 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 46987 # Simulator instruction rate (inst/s)
+host_op_rate 46985 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 89318295 # Simulator tick rate (ticks/s)
+host_mem_usage 231368 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
+sim_insts 12745 # Number of instructions simulated
+sim_ops 12745 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1648238717 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 927134278 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2575372996 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1648238717 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1648238717 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1648238717 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 927134278 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2575372996 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 975 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 82 # Per bank write bursts
+system.physmem.perBankRdBursts::1 153 # Per bank write bursts
+system.physmem.perBankRdBursts::2 77 # Per bank write bursts
+system.physmem.perBankRdBursts::3 60 # Per bank write bursts
+system.physmem.perBankRdBursts::4 87 # Per bank write bursts
+system.physmem.perBankRdBursts::5 49 # Per bank write bursts
+system.physmem.perBankRdBursts::6 32 # Per bank write bursts
+system.physmem.perBankRdBursts::7 49 # Per bank write bursts
+system.physmem.perBankRdBursts::8 42 # Per bank write bursts
+system.physmem.perBankRdBursts::9 39 # Per bank write bursts
+system.physmem.perBankRdBursts::10 30 # Per bank write bursts
+system.physmem.perBankRdBursts::11 33 # Per bank write bursts
+system.physmem.perBankRdBursts::12 15 # Per bank write bursts
+system.physmem.perBankRdBursts::13 121 # Per bank write bursts
+system.physmem.perBankRdBursts::14 70 # Per bank write bursts
+system.physmem.perBankRdBursts::15 36 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 24081000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 975 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 370 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 271.926267 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 156.688517 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 360.951821 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 92 42.40% 42.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 33 15.21% 57.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 21 9.68% 67.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 20 9.22% 76.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 3 1.38% 77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 8 3.69% 81.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 3 1.38% 82.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 4 1.84% 84.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 4 1.84% 86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 4 1.84% 88.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 5 2.30% 90.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 4 1.84% 92.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 2 0.92% 93.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896 2 0.92% 94.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 3 1.38% 95.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 1 0.46% 96.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408 2 0.92% 97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536 2 0.92% 98.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600 1 0.46% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 2 0.92% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304 1 0.46% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation
+system.physmem.totQLat 9442250 # Total ticks spent queuing
+system.physmem.totMemAccLat 31257250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 16940000 # Total ticks spent accessing banks
+system.physmem.avgQLat 9684.36 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 17374.36 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 32058.72 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2575.37 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2575.37 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 20.12 # Data bus utilization in percentage
+system.physmem.busUtilRead 20.12 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 758 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 77.74 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 24698.46 # Average gap between requests
+system.physmem.pageHitRate 77.74 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 0.09 # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput 2575372996 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 829 # Transaction distribution
+system.membus.trans_dist::ReadResp 829 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 62400 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 5.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 37.4 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 6676 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4747 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 873 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 18.390562 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4112 # DTB read hits
-system.cpu.dtb.read_misses 99 # DTB read misses
+system.cpu.dtb.read_hits 4587 # DTB read hits
+system.cpu.dtb.read_misses 111 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4211 # DTB read accesses
-system.cpu.dtb.write_hits 2113 # DTB write hits
-system.cpu.dtb.write_misses 55 # DTB write misses
+system.cpu.dtb.read_accesses 4698 # DTB read accesses
+system.cpu.dtb.write_hits 2013 # DTB write hits
+system.cpu.dtb.write_misses 86 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2168 # DTB write accesses
-system.cpu.dtb.data_hits 6225 # DTB hits
-system.cpu.dtb.data_misses 154 # DTB misses
+system.cpu.dtb.write_accesses 2099 # DTB write accesses
+system.cpu.dtb.data_hits 6600 # DTB hits
+system.cpu.dtb.data_misses 197 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6379 # DTB accesses
-system.cpu.itb.fetch_hits 5262 # ITB hits
-system.cpu.itb.fetch_misses 46 # ITB misses
+system.cpu.dtb.data_accesses 6797 # DTB accesses
+system.cpu.itb.fetch_hits 5374 # ITB hits
+system.cpu.itb.fetch_misses 57 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5308 # ITB accesses
+system.cpu.itb.fetch_accesses 5431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 27948 # number of cpu cycles simulated
+system.cpu.numCycles 48460 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6404 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3641 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1747 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4779 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 907 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 237 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 1564 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 36319 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6404 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1684 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 6095 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1819 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5262 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 778 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 22184 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.637171 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.955550 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 37128 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 6222 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5374 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 29555 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.256234 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.686456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 16089 72.53% 72.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 484 2.18% 74.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 383 1.73% 76.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 489 2.20% 78.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 412 1.86% 80.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 381 1.72% 82.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 471 2.12% 84.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 577 2.60% 86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2898 13.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23333 78.95% 78.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 457 1.55% 87.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 520 1.76% 89.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3045 10.30% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 22184 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.229140 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.299521 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 30972 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4872 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5207 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2493 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 640 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 31709 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 698 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2493 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 31718 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2312 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 672 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4929 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1950 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 29261 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1965 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 22098 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 36589 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 36555 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 12932 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 50 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 5419 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2664 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1324 # Number of stores inserted to the mem dependence unit.
+system.cpu.fetch.rateDist::total 29555 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.766158 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 40476 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9889 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5340 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 489 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2737 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2737 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 41177 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6164 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 5023 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2245 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 30189 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 37141 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 6114 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2650 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1324 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 24 # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads 3034 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 25756 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 47 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21797 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11896 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6581 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 22184 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.982555 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.521995 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 26322 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 29555 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.731721 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.328495 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13300 59.95% 59.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3017 13.60% 73.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2291 10.33% 83.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1563 7.05% 90.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1046 4.72% 95.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 585 2.64% 98.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 293 1.32% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 70 0.32% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 19 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 20216 68.40% 68.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3350 11.33% 79.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2622 8.87% 88.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1591 5.38% 93.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1010 3.42% 97.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 22184 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 29555 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 16 8.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 115 57.50% 65.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 69 34.50% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 107 57.84% 62.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 69 37.30% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7481 68.23% 68.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2338 21.32% 89.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1141 10.41% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7076 65.52% 65.54% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2585 23.94% 89.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1134 10.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10965 # Type of FU issued
+system.cpu.iq.FU_type_0::total 10800 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7346 67.82% 67.84% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.85% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.86% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2331 21.52% 89.38% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1150 10.62% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7138 65.93% 65.95% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.96% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.96% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2586 23.89% 89.87% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10832 # Type of FU issued
-system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu 14827 68.02% 68.04% # Type of FU issued
-system.cpu.iq.FU_type::IntMult 2 0.01% 68.05% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv 0 0.00% 68.05% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdMult 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued
-system.cpu.iq.FU_type::MemRead 4669 21.42% 89.49% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite 2291 10.51% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::total 21797 # Type of FU issued
-system.cpu.iq.rate 0.779913 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 107 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 200 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.004909 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.009176 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 66052 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 37703 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19403 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total 10826 # Type of FU issued
+system.cpu.iq.FU_type::total 21626 0.00% 0.00% # Type of FU issued
+system.cpu.iq.rate 0.446265 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 88 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 97 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 185 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 73081 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 18684 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21971 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21785 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1479 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 459 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1787 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 481 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1465 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 459 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1851 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 407 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2493 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 461 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25944 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 945 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5314 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2648 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 47 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 326 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1573 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20270 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2100 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2134 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4234 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1527 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2737 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 6004 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20163 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2365 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4716 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 72 # number of nop insts executed
-system.cpu.iew.exec_nop::1 69 # number of nop insts executed
-system.cpu.iew.exec_nop::total 141 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3199 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3222 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6421 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1640 # Number of branches executed
-system.cpu.iew.exec_branches::1 1645 # Number of branches executed
-system.cpu.iew.exec_branches::total 3285 # Number of branches executed
-system.cpu.iew.exec_stores::0 1099 # Number of stores executed
-system.cpu.iew.exec_stores::1 1088 # Number of stores executed
-system.cpu.iew.exec_stores::total 2187 # Number of stores executed
-system.cpu.iew.exec_rate 0.725276 # Inst execution rate
-system.cpu.iew.wb_sent::0 9893 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9800 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19693 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9771 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9652 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19423 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5068 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5042 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10110 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6625 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6584 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13209 # num instructions consuming a value
+system.cpu.iew.exec_nop::0 109 # number of nop insts executed
+system.cpu.iew.exec_nop::1 90 # number of nop insts executed
+system.cpu.iew.exec_nop::total 199 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3412 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6829 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1584 # Number of branches executed
+system.cpu.iew.exec_branches::1 1595 # Number of branches executed
+system.cpu.iew.exec_branches::total 3179 # Number of branches executed
+system.cpu.iew.exec_stores::0 1066 # Number of stores executed
+system.cpu.iew.exec_stores::1 1047 # Number of stores executed
+system.cpu.iew.exec_stores::total 2113 # Number of stores executed
+system.cpu.iew.exec_rate 0.416075 # Inst execution rate
+system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9371 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 18704 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 4798 # num instructions producing a value
+system.cpu.iew.wb_producers::1 4830 # num instructions producing a value
+system.cpu.iew.wb_producers::total 9628 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6320 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 12567 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.349614 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.345356 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.193376 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.385968 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.764241 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.766134 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 13040 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1358 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 22111 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.579214 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.379258 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 29488 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.433363 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.196034 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 16588 75.02% 75.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2733 12.36% 87.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1194 5.40% 92.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 519 2.35% 95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 313 1.42% 96.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 257 1.16% 97.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 189 0.85% 98.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 86 0.39% 98.95% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 22111 # Number of insts commited each cycle
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-system.cpu.commit.committedInsts::1 6404 # Number of instructions committed
-system.cpu.commit.committedInsts::total 12807 # Number of instructions committed
-system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed
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system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
-system.cpu.commit.refs::0 2050 # Number of memory references committed
-system.cpu.commit.refs::1 2050 # Number of memory references committed
-system.cpu.commit.refs::total 4100 # Number of memory references committed
-system.cpu.commit.loads::0 1185 # Number of loads committed
-system.cpu.commit.loads::1 1185 # Number of loads committed
-system.cpu.commit.loads::total 2370 # Number of loads committed
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system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
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-system.cpu.commit.branches::1 1051 # Number of branches committed
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system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
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system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 5764 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts::0 6386 # Number of Instructions Simulated
-system.cpu.committedInsts::1 6387 # Number of Instructions Simulated
-system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
-system.cpu.cpi::0 4.376448 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 4.375763 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.188053 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.228496 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.228532 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.457027 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 25651 # number of integer regfile reads
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+system.cpu.idleCycles 18905 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
+system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
+system.cpu.cpi::0 7.603954 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 7.605148 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.802275 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_reads 16 # number of floating regfile reads
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system.cpu.misc_regfile_writes 2 # number of misc regfile writes
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency
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+system.cpu.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements::0 0 # number of replacements
+system.cpu.dcache.tags.replacements::1 0 # number of replacements
+system.cpu.dcache.tags.replacements::total 0 # number of replacements
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+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff