stats: Rename num_syscalls to numSyscalls in the reference stats.
[gem5.git] / tests / quick / se / 40.m5threads-test-atomic / ref / sparc / linux / simple-timing-mp / stats.txt
index 704fea740fafad08a4ca30c11c73fa009daa4664..bdf146296749308e265679b4ce70e43966b80811 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000263                       # Number of seconds simulated
-sim_ticks                                   262794500                       # Number of ticks simulated
-final_tick                                  262794500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   263409500                       # Number of ticks simulated
+final_tick                                  263409500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 985745                       # Simulator instruction rate (inst/s)
-host_op_rate                                   985721                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              390370221                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283880                       # Number of bytes of host memory used
-host_seconds                                     0.67                       # Real time elapsed on the host
-sim_insts                                      663567                       # Number of instructions simulated
-sim_ops                                        663567                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 870162                       # Simulator instruction rate (inst/s)
+host_op_rate                                   870149                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              345251596                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264052                       # Number of bytes of host memory used
+host_seconds                                     0.76                       # Real time elapsed on the host
+sim_insts                                      663871                       # Number of instructions simulated
+sim_ops                                        663871                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data              960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst             3712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data             1472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst               64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         3776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst         3712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst           64                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                59                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data                15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                58                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data                23                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            69407845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            40183489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            14368642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             5357799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              487073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             3653044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             1948290                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3896581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               139302763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       69407845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       14368642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         487073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        1948290                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           86211850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           69407845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           40183489                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           14368642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            5357799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             487073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            3653044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            1948290                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3896581                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              139302763                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    139302763                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 430                       # Transaction distribution
-system.membus.trans_dist::ReadResp                430                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1559                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1559                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               36608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  36608                       # Total data (bytes)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              852296                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            5420500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.1                       # Layer utilization (%)
+system.physmem.bw_read::cpu0.inst            69245794                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            40089670                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             2429677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             3644515                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            14092127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             5588257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst              242968                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             3644515                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               138977524                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       69245794                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst        2429677                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       14092127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst         242968                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           86010565                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           69245794                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           40089670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            2429677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3644515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           14092127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            5588257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst             242968                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            3644515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              138977524                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  349.046072                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      429                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.843823                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.889005                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      231.790437                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       54.207948                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       51.556673                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        6.123914                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst        1.773020                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        0.843760                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        1.030292                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.831024                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.003537                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000827                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000787                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000093                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000027                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.005326                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          429                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.006546                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    15709                       # Number of tag accesses
-system.l2c.tags.data_accesses                   15709                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                354                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
-system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 300                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 354                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                300                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                354                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                8                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             15                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                66                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                23                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               66                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               23                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               16                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
-system.l2c.overall_misses::total                  592                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     14927000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      3451500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      3434500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data       418000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst       595000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data       103000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       465000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data       104500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       23498500                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      5174000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       800500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       746000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       730000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      7450500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     14927000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data      8625500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      3434500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1218500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       595000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data       849000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       465000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       834500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        30949000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     14927000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data      8625500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      3434500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1218500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       595000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data       849000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       465000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       834500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       30949000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           15                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.180328                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.727273                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.032787                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.269461                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.974684                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.180328                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.884615                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.032787                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.024523                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.326711                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.180328                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.884615                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.032787                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.326711                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data        52250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data        51500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data        52250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52218.888889                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52468.309859                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52278.716216                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52278.716216                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.inst            10                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 20                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst           59                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst            8                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           15                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           15                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           19                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data           15                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data           14                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           59                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            8                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data           16                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           59                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            8                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data           16                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11414500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2640000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      2368500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       320000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     17223000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1120000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       600499                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       600000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       763992                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      3084491                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3964000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       617000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       576500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       560000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      5717500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     11414500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data      6604000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      2368500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data       897000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data       616500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       320000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       640000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     22940500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     11414500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data      6604000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      2368500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data       897000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data       616500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       320000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       640000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     22940500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.636364                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005464                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.090909                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.021798                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.974684                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005464                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.021798                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005464                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.021798                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data        41100                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40105.769231                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data        41100                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40105.769231                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.toL2Bus.throughput                   646588875                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq               2225                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2225                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             274                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            274                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              429                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             429                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side          934                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          580                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          355                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          352                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          734                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          401                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  4820                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        23424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        23424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        23488                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total             116032                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus                116032                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           53888                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            1473490                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy           2101500                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           1430481                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1650488                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           1157483                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1651988                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           1147981                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1651999                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.6                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           1327473                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.5                       # Layer utilization (%)
-system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          525589                       # number of cpu cycles simulated
+system.cpu0.workload.numSyscalls                   89                       # Number of system calls
+system.cpu0.pwrStateResidencyTicks::ON      263409500                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                          526819                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     158574                       # Number of instructions committed
-system.cpu0.committedOps                       158574                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               109208                       # Number of integer alu accesses
+system.cpu0.committedInsts                     158244                       # Number of instructions committed
+system.cpu0.committedOps                       158244                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               108988                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        26032                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      109208                       # number of integer instructions
+system.cpu0.num_conditional_control_insts        25977                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      108988                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             315782                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110814                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads             315122                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            110594                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        74021                       # number of memory refs
-system.cpu0.num_load_insts                      49007                       # Number of load instructions
-system.cpu0.num_store_insts                     25014                       # Number of store instructions
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    525589                       # Number of busy cycles
-system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.Branches                            26897                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                23624     14.89%     14.89% # Class of executed instruction
-system.cpu0.op_class::IntAlu                    60907     38.39%     53.29% # Class of executed instruction
+system.cpu0.num_mem_refs                        73856                       # number of memory refs
+system.cpu0.num_load_insts                      48897                       # Number of load instructions
+system.cpu0.num_store_insts                     24959                       # Number of store instructions
+system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
+system.cpu0.num_busy_cycles              526818.998000                       # Number of busy cycles
+system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
+system.cpu0.Branches                            26842                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                23569     14.89%     14.89% # Class of executed instruction
+system.cpu0.op_class::IntAlu                    60797     38.40%     53.29% # Class of executed instruction
 system.cpu0.op_class::IntMult                       0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatMult                     0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatMultAcc                  0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatDiv                      0      0.00%     53.29% # Class of executed instruction
+system.cpu0.op_class::FloatMisc                     0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatSqrt                     0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::SimdAdd                       0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::SimdAddAcc                    0      0.00%     53.29% # Class of executed instruction
@@ -591,120 +119,40 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.29% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::MemRead                   49091     30.95%     84.23% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  25014     15.77%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                   48981     30.94%     84.23% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  24959     15.77%    100.00% # Class of executed instruction
+system.cpu0.op_class::FloatMemRead                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::FloatMemWrite                 0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    158636                       # Class of executed instruction
-system.cpu0.icache.tags.replacements              215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          212.401822                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             158170                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           338.693790                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   212.401822                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.414847                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.414847                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           159104                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          159104                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       158170                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         158170                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       158170                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          158170                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       158170                       # number of overall hits
-system.cpu0.icache.overall_hits::total         158170                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
-system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18148000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     18148000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     18148000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     18148000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     18148000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     18148000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       158637                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       158637                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       158637                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       158637                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       158637                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       158637                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002944                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002944                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002944                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002944                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002944                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002944                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38860.813704                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38860.813704                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17214000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     17214000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17214000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     17214000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17214000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     17214000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002944                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.002944                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002944                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.002944                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.op_class::total                    158306                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          145.571924                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs              73489                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          144.946606                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs              73324                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           440.053892                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           439.065868                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.571924                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.284320                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.284320                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   144.946606                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.283099                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.283099                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           296317                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          296317                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        48827                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          48827                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        24780                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         24780                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           295657                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          295657                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data        48717                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          48717                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        24725                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         24725                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        73607                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           73607                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        73607                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          73607                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data        73442                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           73442                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        73442                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          73442                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data          170                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
@@ -715,54 +163,52 @@ system.cpu0.dcache.demand_misses::cpu0.data          353                       #
 system.cpu0.dcache.demand_misses::total           353                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data          353                       # number of overall misses
 system.cpu0.dcache.overall_misses::total          353                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4586981                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total      4586981                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6974000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      6974000                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       360500                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       360500                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     11560981                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     11560981                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     11560981                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     11560981                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        48997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        48997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        24963                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        24963                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4701000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total      4701000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6585500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total      6585500                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       400000                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       400000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     11286500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     11286500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     11286500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     11286500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        48887                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        48887                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        24908                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        24908                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        73960                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        73960                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        73960                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        73960                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003470                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003470                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007331                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007331                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data        73795                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        73795                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        73795                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        73795                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003477                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.003477                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007347                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007347                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004773                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.004773                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004773                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.004773                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391                       # average overall miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004784                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.004784                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004784                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.004784                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          170                       # number of ReadReq MSHR misses
@@ -775,837 +221,1439 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data          353
 system.cpu0.dcache.demand_mshr_misses::total          353                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          353                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          353                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4237019                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4237019                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6608000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6608000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       308500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       308500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10845019                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     10845019                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10845019                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     10845019                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003470                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003470                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007331                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007331                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4531000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4531000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6402500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6402500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       374000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       374000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10933500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     10933500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10933500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     10933500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003477                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003477                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007347                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007347                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004773                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.004773                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004773                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.004773                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          525588                       # number of cpu cycles simulated
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004784                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.004784                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004784                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.004784                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819                       # average overall mshr miss latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements              215                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          211.173601                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             157840                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           337.987152                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   211.173601                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.412448                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.412448                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses           158774                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          158774                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst       157840                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         157840                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       157840                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          157840                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       157840                       # number of overall hits
+system.cpu0.icache.overall_hits::total         157840                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
+system.cpu0.icache.overall_misses::total          467                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     20426000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     20426000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     20426000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     20426000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     20426000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     20426000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       158307                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       158307                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       158307                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       158307                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       158307                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       158307                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002950                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.002950                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002950                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.002950                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002950                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.002950                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 43738.758030                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 43738.758030                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks          215                       # number of writebacks
+system.cpu0.icache.writebacks::total              215                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     19959000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     19959000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     19959000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     19959000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     19959000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     19959000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002950                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.002950                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.002950                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030                       # average overall mshr miss latency
+system.cpu1.pwrStateResidencyTicks::ON      263409500                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                          526818                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     163471                       # Number of instructions committed
-system.cpu1.committedOps                       163471                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               111731                       # Number of integer alu accesses
+system.cpu1.committedInsts                     169340                       # Number of instructions committed
+system.cpu1.committedOps                       169340                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses               111465                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        29880                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      111731                       # number of integer instructions
+system.cpu1.num_conditional_control_insts        32946                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      111465                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             289610                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            111151                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads             276307                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            104671                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        58020                       # number of memory refs
-system.cpu1.num_load_insts                      41540                       # Number of load instructions
-system.cpu1.num_store_insts                     16480                       # Number of store instructions
-system.cpu1.num_idle_cycles              69346.869795                       # Number of idle cycles
-system.cpu1.num_busy_cycles              456241.130205                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.868058                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.131942                       # Percentage of idle cycles
-system.cpu1.Branches                            31528                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                22316     13.65%     13.65% # Class of executed instruction
-system.cpu1.op_class::IntAlu                    75095     45.93%     59.58% # Class of executed instruction
-system.cpu1.op_class::IntMult                       0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.58% # Class of executed instruction
-system.cpu1.op_class::MemRead                   49612     30.34%     89.92% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  16480     10.08%    100.00% # Class of executed instruction
+system.cpu1.num_mem_refs                        54688                       # number of memory refs
+system.cpu1.num_load_insts                      41399                       # Number of load instructions
+system.cpu1.num_store_insts                     13289                       # Number of store instructions
+system.cpu1.num_idle_cycles              74658.860000                       # Number of idle cycles
+system.cpu1.num_busy_cycles              452159.140000                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.858283                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.141717                       # Percentage of idle cycles
+system.cpu1.Branches                            34599                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                25380     14.98%     14.98% # Class of executed instruction
+system.cpu1.op_class::IntAlu                    74993     44.28%     59.26% # Class of executed instruction
+system.cpu1.op_class::IntMult                       0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatMultAcc                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatMisc                     0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.26% # Class of executed instruction
+system.cpu1.op_class::MemRead                   55710     32.89%     92.15% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  13289      7.85%    100.00% # Class of executed instruction
+system.cpu1.op_class::FloatMemRead                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::FloatMemWrite                 0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    163503                       # Class of executed instruction
+system.cpu1.op_class::total                    169372                       # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements                0                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse           26.434544                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              28854                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           994.965517                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.434544                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051630                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.051630                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           218970                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          218970                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data        41227                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          41227                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        13113                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         13113                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        54340                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           54340                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        54340                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          54340                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          164                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          164                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          105                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          269                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           269                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          269                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          269                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      1132500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      1132500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1426000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      1426000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       250000                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       250000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      2558500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      2558500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      2558500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      2558500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        41391                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        41391                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        13218                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        13218                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           69                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        54609                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        54609                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        54609                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        54609                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003962                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.003962                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.007944                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.007944                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.811594                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.811594                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004926                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.004926                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004926                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.004926                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data  6905.487805                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total  6905.487805                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4464.285714                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total  4464.285714                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data  9511.152416                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total  9511.152416                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data  9511.152416                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total  9511.152416                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          164                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          164                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          269                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          269                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          269                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          269                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data       968500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total       968500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1321000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1321000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       194000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       194000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2289500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      2289500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2289500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      2289500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003962                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003962                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.007944                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.007944                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.811594                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.811594                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004926                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.004926                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004926                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.004926                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  5905.487805                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  5905.487805                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3464.285714                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3464.285714                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  8511.152416                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total  8511.152416                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  8511.152416                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total  8511.152416                       # average overall mshr miss latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
 system.cpu1.icache.tags.replacements              280                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           70.017504                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             163138                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           66.813763                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             169007                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           445.732240                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           461.767760                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    70.017504                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.136753                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.136753                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    66.813763                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.130496                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.130496                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           163870                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          163870                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       163138                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         163138                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       163138                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          163138                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       163138                       # number of overall hits
-system.cpu1.icache.overall_hits::total         163138                       # number of overall hits
+system.cpu1.icache.tags.tag_accesses           169739                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          169739                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst       169007                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         169007                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       169007                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          169007                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       169007                       # number of overall hits
+system.cpu1.icache.overall_hits::total         169007                       # number of overall hits
 system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
 system.cpu1.icache.overall_misses::total          366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7544988                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7544988                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7544988                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7544988                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7544988                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7544988                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       163504                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       163504                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       163504                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       163504                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       163504                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       163504                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002238                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002238                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002238                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002238                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002238                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002238                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 20614.721311                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 20614.721311                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5703000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      5703000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      5703000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      5703000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      5703000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      5703000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       169373                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       169373                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       169373                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       169373                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       169373                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       169373                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002161                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.002161                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002161                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.002161                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002161                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.002161                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15581.967213                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15581.967213                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks::writebacks          280                       # number of writebacks
+system.cpu1.icache.writebacks::total              280                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
 system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
 system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6806012                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      6806012                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6806012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      6806012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6806012                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      6806012                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002238                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002238                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002238                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.002238                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002238                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.002238                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           27.720196                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              35348                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1178.266667                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    27.720196                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.054141                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.054141                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           232288                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          232288                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        41378                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          41378                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        16307                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         16307                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           11                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        57685                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           57685                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        57685                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          57685                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          154                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          154                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          109                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           51                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          263                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           263                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          263                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          263                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2494983                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      2494983                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1979500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      1979500                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       209500                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       209500                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      4474483                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      4474483                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      4474483                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      4474483                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        41532                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        41532                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        16416                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        16416                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           62                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           62                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        57948                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        57948                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        57948                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        57948                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003708                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.003708                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.006640                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.006640                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.822581                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.822581                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004539                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.004539                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004539                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.004539                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4107.843137                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  4107.843137                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          154                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          154                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          109                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           51                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          263                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          263                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2170017                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2170017                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1761500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1761500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       107500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       107500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3931517                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3931517                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3931517                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3931517                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003708                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003708                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.006640                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.006640                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004539                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.004539                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004539                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.004539                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  2107.843137                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  2107.843137                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          525588                       # number of cpu cycles simulated
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5337000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      5337000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5337000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      5337000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5337000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      5337000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002161                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002161                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002161                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.002161                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002161                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.002161                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213                       # average overall mshr miss latency
+system.cpu2.pwrStateResidencyTicks::ON      263409500                       # Cumulative time (in ticks) in various power states
+system.cpu2.numCycles                          526819                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     164866                       # Number of instructions committed
-system.cpu2.committedOps                       164866                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               112988                       # Number of integer alu accesses
+system.cpu2.committedInsts                     165892                       # Number of instructions committed
+system.cpu2.committedOps                       165892                       # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses               110657                       # Number of integer alu accesses
 system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        29949                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      112988                       # number of integer instructions
+system.cpu2.num_conditional_control_insts        31626                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      110657                       # number of integer instructions
 system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             294363                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            112900                       # number of times the integer registers were written
+system.cpu2.num_int_register_reads             278357                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            106099                       # number of times the integer registers were written
 system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        59208                       # number of memory refs
-system.cpu2.num_load_insts                      42171                       # Number of load instructions
-system.cpu2.num_store_insts                     17037                       # Number of store instructions
-system.cpu2.num_idle_cycles              69603.869305                       # Number of idle cycles
-system.cpu2.num_busy_cycles              455984.130695                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.867570                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.132430                       # Percentage of idle cycles
-system.cpu2.Branches                            31596                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                22386     13.58%     13.58% # Class of executed instruction
-system.cpu2.op_class::IntAlu                    75723     45.92%     59.50% # Class of executed instruction
-system.cpu2.op_class::IntMult                       0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.50% # Class of executed instruction
-system.cpu2.op_class::MemRead                   49752     30.17%     89.67% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  17037     10.33%    100.00% # Class of executed instruction
+system.cpu2.num_mem_refs                        55200                       # number of memory refs
+system.cpu2.num_load_insts                      40995                       # Number of load instructions
+system.cpu2.num_store_insts                     14205                       # Number of store instructions
+system.cpu2.num_idle_cycles              74930.001716                       # Number of idle cycles
+system.cpu2.num_busy_cycles              451888.998284                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.857769                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.142231                       # Percentage of idle cycles
+system.cpu2.Branches                            33279                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                24060     14.50%     14.50% # Class of executed instruction
+system.cpu2.op_class::IntAlu                    74589     44.95%     59.45% # Class of executed instruction
+system.cpu2.op_class::IntMult                       0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatMultAcc                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatMisc                     0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.45% # Class of executed instruction
+system.cpu2.op_class::MemRead                   53070     31.98%     91.44% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  14205      8.56%    100.00% # Class of executed instruction
+system.cpu2.op_class::FloatMemRead                  0      0.00%    100.00% # Class of executed instruction
+system.cpu2.op_class::FloatMemWrite                 0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    164898                       # Class of executed instruction
+system.cpu2.op_class::total                    165924                       # Class of executed instruction
+system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu2.dcache.tags.replacements                0                       # number of replacements
+system.cpu2.dcache.tags.tagsinuse           27.420509                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              30687                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1058.172414                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.420509                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.053556                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.053556                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           221019                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          221019                       # Number of data accesses
+system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu2.dcache.ReadReq_hits::cpu2.data        40826                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          40826                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        14029                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         14029                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        54855                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           54855                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        54855                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          54855                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          162                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          105                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           56                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          267                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           267                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          267                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          267                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      1409000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      1409000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      1485000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      1485000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       251000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       251000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      2894000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      2894000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      2894000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      2894000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        40988                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        40988                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        14134                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        14134                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        55122                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        55122                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        55122                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        55122                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003952                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.003952                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.007429                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.007429                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.811594                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.811594                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004844                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.004844                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004844                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.004844                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  8697.530864                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total  8697.530864                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4482.142857                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total  4482.142857                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311                       # average overall miss latency
+system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           56                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1247000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1247000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1380000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1380000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       195000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       195000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      2627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2627000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      2627000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003952                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003952                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.007429                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.007429                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.811594                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.811594                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004844                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.004844                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004844                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.004844                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  7697.530864                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  7697.530864                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  3482.142857                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  3482.142857                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9838.951311                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9838.951311                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9838.951311                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9838.951311                       # average overall mshr miss latency
+system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
 system.cpu2.icache.tags.replacements              280                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           67.624960                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             164533                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.tagsinuse           69.231273                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             165559                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs           449.543716                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.avg_refs           452.346995                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    67.624960                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.132080                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.132080                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    69.231273                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.135217                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.135217                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           165265                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          165265                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       164533                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         164533                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       164533                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          164533                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       164533                       # number of overall hits
-system.cpu2.icache.overall_hits::total         164533                       # number of overall hits
+system.cpu2.icache.tags.tag_accesses           166291                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          166291                       # Number of data accesses
+system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu2.icache.ReadReq_hits::cpu2.inst       165559                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         165559                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       165559                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          165559                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       165559                       # number of overall hits
+system.cpu2.icache.overall_hits::total         165559                       # number of overall hits
 system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
 system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
 system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
 system.cpu2.icache.overall_misses::total          366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5252488                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      5252488                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      5252488                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      5252488                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      5252488                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      5252488                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       164899                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       164899                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       164899                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       164899                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       164899                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       164899                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002220                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002220                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002220                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002220                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002220                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002220                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 14351.060109                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 14351.060109                       # average overall miss latency
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8164000                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      8164000                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      8164000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      8164000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      8164000                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      8164000                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       165925                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       165925                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       165925                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       165925                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       165925                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       165925                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002206                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.002206                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002206                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.002206                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002206                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.002206                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 22306.010929                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 22306.010929                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu2.icache.writebacks::writebacks          280                       # number of writebacks
+system.cpu2.icache.writebacks::total              280                       # number of writebacks
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
 system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
 system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4510512                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      4510512                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4510512                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      4510512                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4510512                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      4510512                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002220                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.002220                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002220                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.002220                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           26.763890                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              36347                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1253.344828                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.763890                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.052273                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.052273                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           237038                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          237038                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42011                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42011                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        16865                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         16865                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           10                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        58876                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           58876                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        58876                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          58876                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          152                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          152                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          110                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          110                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           50                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           50                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          262                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           262                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          262                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          262                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2128981                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      2128981                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      1929500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      1929500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       204500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       204500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      4058481                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      4058481                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      4058481                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      4058481                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        42163                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        42163                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        16975                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        16975                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           60                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           60                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        59138                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        59138                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        59138                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        59138                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003605                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003605                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006480                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.006480                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004430                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004430                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004430                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004430                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data         4090                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total         4090                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496                       # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          152                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          110                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          110                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           50                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           50                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          262                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          262                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1809019                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1809019                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1709500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1709500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       104500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       104500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3518519                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3518519                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3518519                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3518519                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003605                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003605                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.006480                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.006480                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.833333                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.833333                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004430                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.004430                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004430                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.004430                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data         2090                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total         2090                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          525588                       # number of cpu cycles simulated
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7798000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      7798000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7798000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      7798000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7798000                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      7798000                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002206                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002206                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002206                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.002206                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002206                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.002206                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929                       # average overall mshr miss latency
+system.cpu3.pwrStateResidencyTicks::ON      263409500                       # Cumulative time (in ticks) in various power states
+system.cpu3.numCycles                          526818                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     176656                       # Number of instructions committed
-system.cpu3.committedOps                       176656                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               108218                       # Number of integer alu accesses
+system.cpu3.committedInsts                     170395                       # Number of instructions committed
+system.cpu3.committedOps                       170395                       # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses               111057                       # Number of integer alu accesses
 system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        38223                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      108218                       # number of integer instructions
+system.cpu3.num_conditional_control_insts        33676                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      111057                       # number of integer instructions
 system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             242179                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes             89182                       # number of times the integer registers were written
+system.cpu3.num_int_register_reads             271753                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            102596                       # number of times the integer registers were written
 system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        46164                       # number of memory refs
-system.cpu3.num_load_insts                      39753                       # Number of load instructions
-system.cpu3.num_store_insts                      6411                       # Number of store instructions
-system.cpu3.num_idle_cycles              69869.868798                       # Number of idle cycles
-system.cpu3.num_busy_cycles              455718.131202                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.867063                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.132937                       # Percentage of idle cycles
-system.cpu3.Branches                            39890                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                30652     17.35%     17.35% # Class of executed instruction
-system.cpu3.op_class::IntAlu                    73353     41.52%     58.86% # Class of executed instruction
-system.cpu3.op_class::IntMult                       0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     58.86% # Class of executed instruction
-system.cpu3.op_class::MemRead                   66272     37.51%     96.37% # Class of executed instruction
-system.cpu3.op_class::MemWrite                   6411      3.63%    100.00% # Class of executed instruction
+system.cpu3.num_mem_refs                        53550                       # number of memory refs
+system.cpu3.num_load_insts                      41191                       # Number of load instructions
+system.cpu3.num_store_insts                     12359                       # Number of store instructions
+system.cpu3.num_idle_cycles              75201.858967                       # Number of idle cycles
+system.cpu3.num_busy_cycles              451616.141033                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.857253                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.142747                       # Percentage of idle cycles
+system.cpu3.Branches                            35332                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                26110     15.32%     15.32% # Class of executed instruction
+system.cpu3.op_class::IntAlu                    74791     43.88%     59.20% # Class of executed instruction
+system.cpu3.op_class::IntMult                       0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatMultAcc                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatMisc                     0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.20% # Class of executed instruction
+system.cpu3.op_class::MemRead                   57167     33.54%     92.75% # Class of executed instruction
+system.cpu3.op_class::MemWrite                  12359      7.25%    100.00% # Class of executed instruction
+system.cpu3.op_class::FloatMemRead                  0      0.00%    100.00% # Class of executed instruction
+system.cpu3.op_class::FloatMemWrite                 0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    176688                       # Class of executed instruction
+system.cpu3.op_class::total                    170427                       # Class of executed instruction
+system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.tags.replacements                0                       # number of replacements
+system.cpu3.dcache.tags.tagsinuse           25.613981                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              27108                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs           903.600000                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.613981                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050027                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.050027                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           214417                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          214417                       # Number of data accesses
+system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.ReadReq_hits::cpu3.data        41020                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          41020                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        12180                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         12180                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        53200                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           53200                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        53200                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          53200                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          163                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          163                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          105                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           58                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          268                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           268                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          268                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          268                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      1141000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      1141000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1445000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      1445000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       263000                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       263000                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      2586000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      2586000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      2586000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      2586000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        41183                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        41183                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        12285                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        12285                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           72                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           72                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        53468                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        53468                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        53468                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        53468                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003958                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.003958                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.008547                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.008547                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.805556                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.805556                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005012                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.005012                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005012                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.005012                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data         7000                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total         7000                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4534.482759                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total  4534.482759                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data  9649.253731                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total  9649.253731                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data  9649.253731                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total  9649.253731                       # average overall miss latency
+system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          163                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           58                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          268                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          268                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data       978000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total       978000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1340000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1340000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       205000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       205000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2318000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      2318000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2318000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      2318000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003958                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003958                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.008547                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.008547                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.805556                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.805556                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.005012                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.005012                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.005012                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.005012                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data         6000                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total         6000                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3534.482759                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3534.482759                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  8649.253731                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total  8649.253731                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  8649.253731                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total  8649.253731                       # average overall mshr miss latency
+system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
 system.cpu3.icache.tags.replacements              281                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           65.598437                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             176322                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse           64.803703                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             170061                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              367                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs           480.441417                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs           463.381471                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    65.598437                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.128122                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.128122                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    64.803703                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.126570                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.126570                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           177056                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          177056                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       176322                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         176322                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       176322                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          176322                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       176322                       # number of overall hits
-system.cpu3.icache.overall_hits::total         176322                       # number of overall hits
+system.cpu3.icache.tags.tag_accesses           170795                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          170795                       # Number of data accesses
+system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.cpu3.icache.ReadReq_hits::cpu3.inst       170061                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         170061                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       170061                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          170061                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       170061                       # number of overall hits
+system.cpu3.icache.overall_hits::total         170061                       # number of overall hits
 system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
 system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
 system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
 system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
 system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
 system.cpu3.icache.overall_misses::total          367                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5147499                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      5147499                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      5147499                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      5147499                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      5147499                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      5147499                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       176689                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       176689                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       176689                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       176689                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       176689                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       176689                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002077                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002077                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002077                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002077                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002077                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002077                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 14025.882834                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 14025.882834                       # average overall miss latency
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5475500                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      5475500                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      5475500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      5475500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      5475500                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      5475500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       170428                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       170428                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       170428                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       170428                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       170428                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       170428                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002153                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.002153                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002153                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.002153                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002153                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.002153                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 14919.618529                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 14919.618529                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu3.icache.writebacks::writebacks          281                       # number of writebacks
+system.cpu3.icache.writebacks::total              281                       # number of writebacks
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
 system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
 system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4412501                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      4412501                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4412501                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      4412501                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4412501                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      4412501                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002077                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002077                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002077                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.002077                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002077                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.002077                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           25.915086                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              15020                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs           517.931034                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.915086                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050615                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.050615                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           184905                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          184905                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        39563                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          39563                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data         6216                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total          6216                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           19                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        45779                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           45779                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        45779                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          45779                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          183                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          183                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          105                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           69                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           69                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          288                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           288                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          288                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          288                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3156473                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      3156473                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2098500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2098500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       280000                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       280000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      5254973                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      5254973                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      5254973                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      5254973                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        39746                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        39746                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data         6321                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total         6321                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           88                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           88                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        46067                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        46067                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        46067                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        46067                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.004604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.004604                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.016611                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.016611                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.784091                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.784091                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006252                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.006252                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006252                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.006252                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4057.971014                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  4057.971014                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028                       # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          183                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           69                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           69                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          288                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          288                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          288                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          288                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2772527                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2772527                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1888500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1888500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       142000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       142000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4661027                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      4661027                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4661027                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      4661027                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004604                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.016611                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.016611                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.784091                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.784091                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.006252                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.006252                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.006252                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.006252                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  2057.971014                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  2057.971014                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5108500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      5108500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5108500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      5108500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5108500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      5108500                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002153                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002153                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002153                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.002153                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002153                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.002153                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                        0                       # number of replacements
+system.l2c.tags.tagsinuse                  470.663959                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1794                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                      572                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.136364                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::cpu0.inst      230.500098                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data      147.566608                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst        6.217156                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       10.908895                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst       46.660458                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data       17.373358                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        0.877256                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data       10.560130                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::cpu0.inst       0.003517                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.002252                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000095                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000166                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000712                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.000265                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000013                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.000161                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.007182                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          572                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.008728                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    19676                       # Number of tag accesses
+system.l2c.tags.data_accesses                   19676                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks          495                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total             495                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data              30                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              16                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              16                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data              17                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  79                       # number of UpgradeReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst           182                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst           352                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst           301                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst           357                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total              1192                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            3                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               26                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 352                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 301                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   3                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1218                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                352                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                301                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  3                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
+system.l2c.overall_hits::total                   1218                       # number of overall hits
+system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data             14                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data             15                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          285                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst           14                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst           65                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst           10                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total             374                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data           66                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data            2                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data            8                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total             78                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                14                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                65                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data                23                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                10                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   594                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               14                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               16                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst               65                       # number of overall misses
+system.l2c.overall_misses::cpu2.data               23                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst               10                       # number of overall misses
+system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
+system.l2c.overall_misses::total                  594                       # number of overall misses
+system.l2c.ReadExReq_miss_latency::cpu0.data      5991000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data       851500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       911000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       861000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      8614500                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     17251000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst       845000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst      3885000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst       552500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     22533500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data      3993500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data       120000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data       484000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data       120500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total      4718000                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     17251000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data      9984500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst       845000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data       971500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      3885000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1395000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       552500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       981500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        35866000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     17251000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data      9984500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst       845000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data       971500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      3885000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1395000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       552500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       981500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       35866000                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks          495                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total          495                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           17                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data           14                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data           15                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          467                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          366                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          366                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          367                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1566                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data           71                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data           11                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data           11                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data           11                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total          104                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.610278                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.038251                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.177596                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.027248                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.238825                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.929577                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181818                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.727273                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.181818                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.750000                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.038251                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.640000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.177596                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.884615                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.027248                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.327815                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.038251                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.640000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.177596                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.884615                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.027248                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.327815                       # miss rate for overall accesses
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60821.428571                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60733.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data        61500                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 60665.492958                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 60529.824561                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 60357.142857                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 59769.230769                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst        55250                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total        60250                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 60507.575758                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        60000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        60500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        60250                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 60487.179487                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 60529.824561                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 60512.121212                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 60357.142857                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 60718.750000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 59769.230769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 60652.173913                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        55250                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 61343.750000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 60380.471380                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 60529.824561                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 60512.121212                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 60357.142857                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 60718.750000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 59769.230769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 60652.173913                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        55250                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 61343.750000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 60380.471380                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            7                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            9                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 22                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                22                       # number of overall MSHR hits
+system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data           14                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data           15                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          285                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           10                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           58                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            1                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total          354                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data           66                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data            1                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data            8                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data            1                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total           76                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           10                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst           58                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data           23                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           10                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst           58                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data           23                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5001000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       711500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       761000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       721000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      7194500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     14401000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst       510000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      2929500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst        50500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     17891000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      3333500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data        50500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       404000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        50500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total      3838500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     14401000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data      8334500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst       510000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data       762000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst      2929500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data      1165000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst        50500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       771500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     28924000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     14401000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data      8334500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst       510000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data       762000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst      2929500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data      1165000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst        50500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       771500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     28924000                       # number of overall MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.226054                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.727273                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.730769                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        51500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst        51000                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        50500                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        50500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        50500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        50500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        51000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        50800                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        50500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 50566.433566                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        51000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        50800                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        50500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 50566.433566                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests           839                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests          261                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp                430                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              195                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           430                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1405                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1405                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   36608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              261                       # Total snoops (count)
+system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples               839                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     839    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 839                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              587124                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2860000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests         3977                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests         1080                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1895                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    263409500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadResp              2225                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean         1056                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             274                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            274                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              420                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             420                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq          1566                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq          659                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          581                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1012                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          366                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1012                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1015                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          368                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  5868                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        43648                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        41344                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        41344                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        41472                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total                 183616                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                            1028                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                     53312                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples             2919                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.294964                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.172134                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                   1002     34.33%     34.33% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                    753     25.80%     60.12% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    465     15.93%     76.05% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                    699     23.95%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total               2919                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            3053983                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              1.2                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy            700500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy            499498                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy            550995                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy            431976                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy            552491                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy            427974                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy            554986                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy            431477                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------