---------- Begin Simulation Statistics ----------
-sim_seconds 0.000889 # Number of seconds simulated
-sim_ticks 888991000 # Number of ticks simulated
-final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000541 # Number of seconds simulated
+sim_ticks 540820000 # Number of ticks simulated
+final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 170326912 # Simulator tick rate (ticks/s)
-host_mem_usage 278304 # Number of bytes of host memory used
-host_seconds 5.22 # Real time elapsed on the host
+host_tick_rate 46544616 # Simulator tick rate (ticks/s)
+host_mem_usage 216108 # Number of bytes of host memory used
+host_seconds 11.62 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory
-system.physmem.bytes_read::total 628365 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory
-system.physmem.bytes_written::total 439804 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory
+system.physmem.bytes_read::total 664374 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory
+system.physmem.bytes_written::total 470013 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 99131 # number of read accesses completed
-system.cpu0.num_writes 55164 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22535 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks.
+system.cpu0.num_reads 99596 # number of read accesses completed
+system.cpu0.num_writes 55268 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22066 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9783 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60648 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits
+system.cpu0.l1c.overall_hits::total 10040 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses
+system.cpu0.l1c.overall_misses::total 60377 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks
-system.cpu0.l1c.writebacks::total 9979 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks
+system.cpu0.l1c.writebacks::total 9669 # number of writebacks
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+system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses
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+system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses
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+system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses
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+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency
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+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99860 # number of read accesses completed
-system.cpu1.num_writes 55211 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22541 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks.
+system.cpu1.num_reads 98929 # number of read accesses completed
+system.cpu1.num_writes 55238 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22532 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits
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-system.cpu1.l1c.overall_hits::total 9891 # number of overall hits
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-system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses
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-system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses
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-system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60508 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles
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-system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses
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-system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked
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+system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy
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+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses
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+system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits
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+system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses
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+system.cpu1.l1c.overall_misses::total 60475 # number of overall misses
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+system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses)
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+system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses
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+system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses
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+system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses
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+system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks
-system.cpu1.l1c.writebacks::total 9897 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks
+system.cpu1.l1c.writebacks::total 9918 # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable
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+system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses
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+system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles
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+system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses
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+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99820 # number of read accesses completed
-system.cpu2.num_writes 54950 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22307 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks.
+system.cpu2.num_reads 99726 # number of read accesses completed
+system.cpu2.num_writes 55227 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22340 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9993 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60635 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits
+system.cpu2.l1c.overall_hits::total 9766 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses
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+system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses
+system.cpu2.l1c.overall_misses::total 60544 # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks
-system.cpu2.l1c.writebacks::total 9745 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency
+system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks
+system.cpu2.l1c.writebacks::total 9768 # number of writebacks
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+system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses
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+system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses
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+system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable
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+system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable
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+system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses
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+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles
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+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses
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+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99181 # number of read accesses completed
-system.cpu3.num_writes 54913 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22385 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks.
+system.cpu3.num_reads 99494 # number of read accesses completed
+system.cpu3.num_writes 54686 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22431 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9698 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60513 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits
+system.cpu3.l1c.overall_hits::total 9721 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses
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+system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses
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+system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses
+system.cpu3.l1c.overall_misses::total 60568 # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles
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+system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks
-system.cpu3.l1c.writebacks::total 9719 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks
+system.cpu3.l1c.writebacks::total 9871 # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses
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+system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99531 # number of read accesses completed
-system.cpu4.num_writes 55217 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22414 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks.
+system.cpu4.num_reads 99490 # number of read accesses completed
+system.cpu4.num_writes 54928 # number of write accesses completed
+system.cpu4.l1c.tags.replacements 22277 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9858 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60389 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits
+system.cpu4.l1c.overall_hits::total 9837 # number of overall hits
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+system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses
+system.cpu4.l1c.overall_misses::total 60390 # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks
-system.cpu4.l1c.writebacks::total 9784 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency
+system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks
+system.cpu4.l1c.writebacks::total 9949 # number of writebacks
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+system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses
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+system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses
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+system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses
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+system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable
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+system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable
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+system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses
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+system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles
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+system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles
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+system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles
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+system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 100000 # number of read accesses completed
-system.cpu5.num_writes 55296 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22532 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks.
+system.cpu5.num_reads 99495 # number of read accesses completed
+system.cpu5.num_writes 55318 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22409 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits
-system.cpu5.l1c.overall_hits::total 9941 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60368 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits
+system.cpu5.l1c.overall_hits::total 9783 # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses
+system.cpu5.l1c.overall_misses::total 60447 # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks
-system.cpu5.l1c.writebacks::total 9981 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60368 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9842 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5587 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5587 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15429 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15429 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1156614548 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1156614548 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks
+system.cpu5.l1c.writebacks::total 9995 # number of writebacks
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+system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses
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+system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable
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+system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable
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+system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses
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+system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles
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+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles
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+system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles
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+system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses
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+system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 99879 # number of read accesses completed
-system.cpu6.num_writes 55426 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22371 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks.
+system.cpu6.num_reads 100000 # number of read accesses completed
+system.cpu6.num_writes 55059 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22318 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9921 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60654 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits
+system.cpu6.l1c.overall_hits::total 9881 # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses
+system.cpu6.l1c.overall_misses::total 60528 # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles
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+system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks
-system.cpu6.l1c.writebacks::total 9808 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency
+system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks
+system.cpu6.l1c.writebacks::total 9777 # number of writebacks
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+system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses
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+system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses
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+system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses
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+system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses
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+system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable
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+system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable
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+system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses
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+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles
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+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles
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+system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses
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+system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99237 # number of read accesses completed
-system.cpu7.num_writes 54706 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22568 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks.
+system.cpu7.num_reads 99734 # number of read accesses completed
+system.cpu7.num_writes 54921 # number of write accesses completed
+system.cpu7.l1c.tags.replacements 22329 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9873 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses
-system.cpu7.l1c.overall_misses::total 60373 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits
+system.cpu7.l1c.overall_hits::total 9960 # number of overall hits
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+system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses
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+system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles
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+system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses)
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+system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency
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+system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency
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system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 56351 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 19.984951 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9950 # number of writebacks
-system.cpu7.l1c.writebacks::total 9950 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36422 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36422 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23951 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses
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-system.cpu7.l1c.demand_mshr_misses::total 60373 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 60373 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses
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-system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5444 # number of WriteReq MSHR uncacheable
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-system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses
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-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1150841746 # number of ReadReq MSHR miss cycles
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-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1042608279 # number of WriteReq MSHR miss cycles
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-system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2193450025 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 2193450025 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 802753372 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 802753372 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1502766880 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1502766880 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2305520252 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806064 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806064 # mshr miss rate for ReadReq accesses
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-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955708 # mshr miss rate for WriteReq accesses
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-system.cpu7.l1c.demand_mshr_miss_rate::total 0.859451 # mshr miss rate for demand accesses
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-system.cpu7.l1c.overall_mshr_miss_rate::total 0.859451 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494 # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494 # average ReadReq mshr uncacheable latency
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-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485 # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency
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+system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks
+system.cpu7.l1c.writebacks::total 9746 # number of writebacks
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+system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses
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+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 13238 # number of replacements
-system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use
-system.l2c.tags.total_refs 163749 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks.
+system.l2c.tags.replacements 14328 # number of replacements
+system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use
+system.l2c.tags.total_refs 163940 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 731.907933 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.423018 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 6.356158 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.459637 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.505664 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.498026 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.297131 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.613319 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.425290 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.714754 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0 0.006272 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1 0.006207 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu3 0.006353 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4 0.006346 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5 0.006150 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6 0.006458 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7 0.006275 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.765123 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.770508 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 2093442 # Number of tag accesses
-system.l2c.tags.data_accesses 2093442 # Number of data accesses
-system.l2c.Writeback_hits::writebacks 77141 # number of Writeback hits
-system.l2c.Writeback_hits::total 77141 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 278 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 288 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 234 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 250 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 237 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 267 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 288 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 265 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2107 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 1745 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 1822 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 1757 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1774 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1783 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1866 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1759 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1730 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 14236 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0 10764 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1 10818 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2 10858 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3 10852 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4 10715 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5 10815 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6 10778 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7 10709 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 86309 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0 12509 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1 12640 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2 12615 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12626 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 12498 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12681 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12537 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12439 # number of demand (read+write) hits
-system.l2c.demand_hits::total 100545 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0 12509 # number of overall hits
-system.l2c.overall_hits::cpu1 12640 # number of overall hits
-system.l2c.overall_hits::cpu2 12615 # number of overall hits
-system.l2c.overall_hits::cpu3 12626 # number of overall hits
-system.l2c.overall_hits::cpu4 12498 # number of overall hits
-system.l2c.overall_hits::cpu5 12681 # number of overall hits
-system.l2c.overall_hits::cpu6 12537 # number of overall hits
-system.l2c.overall_hits::cpu7 12439 # number of overall hits
-system.l2c.overall_hits::total 100545 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0 2044 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1 2057 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2 2093 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 2098 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 2109 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 2052 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 2068 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 2060 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 16581 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0 4635 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1 4534 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2 4676 # number of ReadExReq misses
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880706 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.884615 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.883264 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.886923 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.869863 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.885969 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 78861 # Transaction distribution
-system.membus.trans_dist::ReadResp 84355 # Transaction distribution
-system.membus.trans_dist::WriteReq 43772 # Transaction distribution
-system.membus.trans_dist::WriteResp 43770 # Transaction distribution
-system.membus.trans_dist::Writeback 6188 # Transaction distribution
-system.membus.trans_dist::CleanEvict 1234 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution
-system.membus.trans_dist::ReadExReq 49401 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3090 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 57121 # Total snoops (count)
-system.membus.snoop_fanout::samples 253876 # Request fanout histogram
+system.membus.trans_dist::ReadReq 78710 # Transaction distribution
+system.membus.trans_dist::ReadResp 84594 # Transaction distribution
+system.membus.trans_dist::WriteReq 43645 # Transaction distribution
+system.membus.trans_dist::WriteResp 43644 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution
+system.membus.trans_dist::CleanEvict 1288 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution
+system.membus.trans_dist::ReadExReq 49324 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3261 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 56843 # Total snoops (count)
+system.membus.snoop_fanout::samples 246442 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 253876 # Request fanout histogram
-system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 246442 # Request fanout histogram
+system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 54.1 # Layer utilization (%)
-system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 35.7 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 335326 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram
+system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 54.9 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 335082 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff