+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.048960 # Number of seconds simulated
+sim_ticks 48960022500 # Number of ticks simulated
+final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1769120 # Simulator instruction rate (inst/s)
+host_op_rate 2262458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1221438298 # Simulator tick rate (ticks/s)
+host_mem_usage 267796 # Number of bytes of host memory used
+host_seconds 40.08 # Real time elapsed on the host
+sim_insts 70913204 # Number of instructions simulated
+sim_ops 90688159 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
+system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
+system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.numSyscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 48960022500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 97920046 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 70913204 # Number of instructions committed
+system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3311620 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
+system.cpu.num_int_insts 81528528 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 141479271 # number of times the integer registers were read
+system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
+system.cpu.num_mem_refs 43422001 # number of memory refs
+system.cpu.num_load_insts 22866262 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 13741468 # Number of branches fetched
+system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
+system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction
+system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction
+system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 90690106 # Class of executed instruction
+system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq 100925158 # Transaction distribution
+system.membus.trans_dist::ReadResp 100941077 # Transaction distribution
+system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
+system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 120930641 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 120930641 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 120930641 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff