---------- Begin Simulation Statistics ----------
-sim_seconds 0.000042 # Number of seconds simulated
-sim_ticks 41751 # Number of ticks simulated
-final_tick 41751 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000043 # Number of seconds simulated
+sim_ticks 43191 # Number of ticks simulated
+final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 456955 # Simulator tick rate (ticks/s)
-host_mem_usage 445744 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 266014 # Simulator tick rate (ticks/s)
+host_mem_usage 386184 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55552 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55552 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49728 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49728 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 868 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 868 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 777 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 777 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1330554957 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1330554957 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1191061292 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1191061292 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2521616249 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2521616249 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 868 # Number of read requests accepted
-system.mem_ctrls.writeReqs 777 # Number of write requests accepted
-system.mem_ctrls.readBursts 868 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 777 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9792 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40448 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55552 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49728 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 123 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 57728 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 51904 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 51904 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 902 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 902 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 811 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 811 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1336574749 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1336574749 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1201731842 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1201731842 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 2538306592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 2538306592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 902 # Number of read requests accepted
+system.mem_ctrls.writeReqs 811 # Number of write requests accepted
+system.mem_ctrls.readBursts 902 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 811 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 47168 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 57728 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 51904 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 130 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 213 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 219 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 227 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 48 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 191 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 198 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 201 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 46 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 41665 # Total gap between requests
+system.mem_ctrls.totGap 43109 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 868 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 902 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 777 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 439 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 276 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 811 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 456 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 281 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 943.460674 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 892.281841 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 207.277759 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 1 1.12% 1.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 1 1.12% 2.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 4 4.49% 6.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3 3.37% 10.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 4.49% 14.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 6 6.74% 21.35% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 70 78.65% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 18.128205 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.885323 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.442608 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 4 10.26% 10.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 17 43.59% 53.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 12 30.77% 84.62% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 89.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 3 7.69% 97.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 2.56% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.205128 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.194457 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.614709 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 35 89.74% 89.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 4 10.26% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8953 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 22538 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.52 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 928 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 868.246553 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 227.729324 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 1 1.06% 1.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 2 2.13% 3.19% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 3 3.19% 6.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 1 1.06% 7.45% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 4 4.26% 11.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 3 3.19% 14.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 17.02% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 3.19% 20.21% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 75 79.79% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 18.125000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 17.875881 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.480256 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 4 10.00% 10.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 17 42.50% 52.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 12 30.00% 82.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 87.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 3 7.50% 95.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-25 1 2.50% 97.50% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.280005 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.853349 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 1 2.50% 90.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 3 7.50% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 8956 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 22959 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3685 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.15 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.52 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1096.02 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 968.79 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1330.55 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1191.06 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.15 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 1092.08 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 966.13 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1336.57 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1201.73 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 16.13 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 8.56 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 7.57 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.65 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.68 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 630 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 624 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 88.11 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.41 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 25.33 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.60 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls.busUtil 16.08 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 8.53 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 7.55 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.63 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 25.46 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 647 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 644 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.79 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 94.57 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 25.17 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 665280 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 369600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 8311680 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 6034176 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 6231168 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 26710200 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 26706780 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 44685456 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 1140.080520 # Core power per rank (mW)
+system.mem_ctrls_0.totalEnergy 44914308 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1146.065527 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 37890 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 37885 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 6487 # delay histogram for all message
-system.ruby.delayHist::mean 2.607369 # delay histogram for all message
-system.ruby.delayHist::stdev 5.331776 # delay histogram for all message
-system.ruby.delayHist | 4997 77.03% 77.03% | 72 1.11% 78.14% | 1050 16.19% 94.33% | 14 0.22% 94.54% | 300 4.62% 99.17% | 2 0.03% 99.20% | 2 0.03% 99.23% | 47 0.72% 99.95% | 0 0.00% 99.95% | 3 0.05% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 6487 # delay histogram for all message
+system.ruby.delayHist::samples 6720 # delay histogram for all message
+system.ruby.delayHist::mean 2.675000 # delay histogram for all message
+system.ruby.delayHist::stdev 5.399947 # delay histogram for all message
+system.ruby.delayHist | 5144 76.55% 76.55% | 51 0.76% 77.31% | 1138 16.93% 94.24% | 8 0.12% 94.36% | 323 4.81% 99.17% | 6 0.09% 99.26% | 0 0.00% 99.26% | 43 0.64% 99.90% | 0 0.00% 99.90% | 7 0.10% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 6720 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 988
-system.ruby.outstanding_req_hist::mean 15.694332
-system.ruby.outstanding_req_hist::gmean 15.587555
-system.ruby.outstanding_req_hist::stdev 1.214439
-system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.40% 1.11% | 2 0.20% 1.32% | 5 0.51% 1.82% | 157 15.89% 17.71% | 813 82.29% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 988
+system.ruby.outstanding_req_hist::samples 1041
+system.ruby.outstanding_req_hist::mean 15.700288
+system.ruby.outstanding_req_hist::gmean 15.598621
+system.ruby.outstanding_req_hist::stdev 1.186661
+system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.48% | 2 0.19% 0.67% | 4 0.38% 1.06% | 2 0.19% 1.25% | 5 0.48% 1.73% | 167 16.04% 17.77% | 856 82.23% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 1041
system.ruby.latency_hist::bucket_size 128
system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 973
-system.ruby.latency_hist::mean 670.474820
-system.ruby.latency_hist::gmean 404.512965
-system.ruby.latency_hist::stdev 282.511489
-system.ruby.latency_hist | 123 12.64% 12.64% | 25 2.57% 15.21% | 6 0.62% 15.83% | 4 0.41% 16.24% | 32 3.29% 19.53% | 325 33.40% 52.93% | 378 38.85% 91.78% | 43 4.42% 96.20% | 29 2.98% 99.18% | 8 0.82% 100.00%
-system.ruby.latency_hist::total 973
+system.ruby.latency_hist::samples 1025
+system.ruby.latency_hist::mean 658.597073
+system.ruby.latency_hist::gmean 361.484818
+system.ruby.latency_hist::stdev 297.350955
+system.ruby.latency_hist | 154 15.02% 15.02% | 24 2.34% 17.37% | 5 0.49% 17.85% | 4 0.39% 18.24% | 32 3.12% 21.37% | 302 29.46% 50.83% | 418 40.78% 91.61% | 49 4.78% 96.39% | 28 2.73% 99.12% | 9 0.88% 100.00%
+system.ruby.latency_hist::total 1025
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 67
+system.ruby.hit_latency_hist::samples 89
system.ruby.hit_latency_hist::mean 1
system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 67 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 67
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 89
system.ruby.miss_latency_hist::bucket_size 128
system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 906
-system.ruby.miss_latency_hist::mean 719.983444
-system.ruby.miss_latency_hist::gmean 630.548999
-system.ruby.miss_latency_hist::stdev 223.799725
-system.ruby.miss_latency_hist | 56 6.18% 6.18% | 25 2.76% 8.94% | 6 0.66% 9.60% | 4 0.44% 10.04% | 32 3.53% 13.58% | 325 35.87% 49.45% | 378 41.72% 91.17% | 43 4.75% 95.92% | 29 3.20% 99.12% | 8 0.88% 100.00%
-system.ruby.miss_latency_hist::total 906
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-system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 918 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 936
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+system.ruby.miss_latency_hist::gmean 632.888578
+system.ruby.miss_latency_hist::stdev 227.503250
+system.ruby.miss_latency_hist | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00%
+system.ruby.miss_latency_hist::total 936
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system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 88 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
-system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits
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+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store
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+system.ruby.l2_cntrl0.L2cache.demand_hits 34 # Number of cache demand hits
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system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
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-system.ruby.delayVCHist.vnet_0 | 1391 54.79% 54.79% | 17 0.67% 55.45% | 768 30.25% 85.70% | 9 0.35% 86.06% | 300 11.82% 97.87% | 2 0.08% 97.95% | 2 0.08% 98.03% | 47 1.85% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 2539 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
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-system.ruby.delayVCHist.vnet_1::stdev 2.345078 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 3317 90.04% 90.04% | 25 0.68% 90.72% | 16 0.43% 91.15% | 39 1.06% 92.21% | 232 6.30% 98.51% | 50 1.36% 99.86% | 5 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 3684 # delay histogram for vnet_1
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+system.ruby.delayVCHist.vnet_0 | 1406 53.66% 53.66% | 9 0.34% 54.01% | 823 31.41% 85.42% | 4 0.15% 85.57% | 323 12.33% 97.90% | 5 0.19% 98.09% | 0 0.00% 98.09% | 43 1.64% 99.73% | 0 0.00% 99.73% | 7 0.27% 100.00% # delay histogram for vnet_0
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+system.ruby.delayVCHist.vnet_1 | 3460 90.53% 90.53% | 42 1.10% 91.63% | 315 8.24% 99.87% | 4 0.10% 99.97% | 0 0.00% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
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system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
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-system.ruby.delayVCHist.vnet_2::mean 0.015152 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.173746 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 262 99.24% 99.24% | 0 0.00% 99.24% | 2 0.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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+system.ruby.delayVCHist.vnet_2 | 278 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
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system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
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system.ruby.LD.hit_latency_hist::mean 1
system.ruby.LD.hit_latency_hist::gmean 1
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-system.ruby.LD.hit_latency_hist::total 3
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system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
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-system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.50% 2.50% | 15 37.50% 40.00% | 20 50.00% 90.00% | 1 2.50% 92.50% | 3 7.50% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.latency_hist::bucket_size 128
system.ruby.ST.latency_hist::max_bucket 1279
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-system.ruby.ST.latency_hist | 83 9.51% 9.51% | 7 0.80% 10.31% | 4 0.46% 10.77% | 4 0.46% 11.23% | 31 3.55% 14.78% | 310 35.51% 50.29% | 358 41.01% 91.29% | 42 4.81% 96.11% | 26 2.98% 99.08% | 8 0.92% 100.00%
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system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
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system.ruby.ST.hit_latency_hist::mean 1
system.ruby.ST.hit_latency_hist::gmean 1
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 63 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 63
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system.ruby.ST.miss_latency_hist::bucket_size 128
system.ruby.ST.miss_latency_hist::max_bucket 1279
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-system.ruby.ST.miss_latency_hist | 20 2.47% 2.47% | 7 0.86% 3.33% | 4 0.49% 3.83% | 4 0.49% 4.32% | 31 3.83% 8.15% | 310 38.27% 46.42% | 358 44.20% 90.62% | 42 5.19% 95.80% | 26 3.21% 99.01% | 8 0.99% 100.00%
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+system.ruby.ST.miss_latency_hist | 19 2.25% 2.25% | 7 0.83% 3.08% | 4 0.47% 3.56% | 4 0.47% 4.03% | 32 3.80% 7.83% | 289 34.28% 42.11% | 404 47.92% 90.04% | 47 5.58% 95.61% | 28 3.32% 98.93% | 9 1.07% 100.00%
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system.ruby.IFETCH.latency_hist::bucket_size 64
system.ruby.IFETCH.latency_hist::max_bucket 639
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-system.ruby.IFETCH.latency_hist | 15 26.32% 26.32% | 22 38.60% 64.91% | 16 28.07% 92.98% | 2 3.51% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 57
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-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 1
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+system.ruby.IFETCH.latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.IFETCH.miss_latency_hist::bucket_size 64
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
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-system.ruby.IFETCH.miss_latency_hist::gmean 91.066566
-system.ruby.IFETCH.miss_latency_hist::stdev 61.178926
-system.ruby.IFETCH.miss_latency_hist | 14 25.00% 25.00% | 22 39.29% 64.29% | 16 28.57% 92.86% | 2 3.57% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 56
-system.ruby.Directory_Controller.Fetch 868 0.00% 0.00%
-system.ruby.Directory_Controller.Data 777 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 777 0.00% 0.00%
+system.ruby.IFETCH.miss_latency_hist::samples 63
+system.ruby.IFETCH.miss_latency_hist::mean 107.476190
+system.ruby.IFETCH.miss_latency_hist::gmean 95.146533
+system.ruby.IFETCH.miss_latency_hist::stdev 52.448702
+system.ruby.IFETCH.miss_latency_hist | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist::total 63
+system.ruby.Directory_Controller.Fetch 902 0.00% 0.00%
+system.ruby.Directory_Controller.Data 811 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 902 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 811 0.00% 0.00%
system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 868 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 777 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 902 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 811 0.00% 0.00%
system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 868 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 777 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 43 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 875 0.00% 0.00%
-system.ruby.L1Cache_Controller.Inv 264 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 12024 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_all_Acks 866 0.00% 0.00%
-system.ruby.L1Cache_Controller.WB_Ack 782 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 56 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 812 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Inv 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement 112 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Inv 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.Inv 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement 39 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 63 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Inv 64 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 745 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 555 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive 40 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks 49 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10564 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks 810 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch 8 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Inv 151 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack 631 0.00% 0.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 151 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GET_INSTR 56 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 810 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 632 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 902 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 811 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 37 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 67 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 927 0.00% 0.00%
+system.ruby.L1Cache_Controller.Inv 278 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 12331 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_Exclusive 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_all_Acks 906 0.00% 0.00%
+system.ruby.L1Cache_Controller.WB_Ack 808 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Ifetch 64 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Store 845 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement 121 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Inv 54 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.Inv 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement 25 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 7 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 82 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Inv 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 785 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Inv 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 386 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive 30 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks 57 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 11011 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks 843 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.Inv 156 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack 652 0.00% 0.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 156 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GET_INSTR 64 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 30 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 844 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 653 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX_old 267 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 574 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 530 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 868 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 203 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 49 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 850 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 780 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old 135 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 574 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 632 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 216 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 16 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 116 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 203 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 40 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 93 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 123 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 780 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 842 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 603 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 569 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 902 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 898 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 208 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 65 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 873 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 61 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 814 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old 134 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 603 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 18 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 653 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 219 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 22 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 898 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 111 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 208 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 121 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 125 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 813 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 20 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 870 0.00% 0.00%
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff