---------- Begin Simulation Statistics ----------
-sim_seconds 0.000358 # Number of seconds simulated
-sim_ticks 357561 # Number of ticks simulated
-final_tick 357561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000054 # Number of seconds simulated
+sim_ticks 54211 # Number of ticks simulated
+final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 908445 # Simulator tick rate (ticks/s)
-host_mem_usage 221056 # Number of bytes of host memory used
-host_seconds 0.39 # Real time elapsed on the host
-system.physmem.bytes_read 0 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 0 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
+host_tick_rate 192824 # Simulator tick rate (ticks/s)
+host_mem_usage 389940 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48256 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 48256 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 754 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 754 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 996402944 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 996402944 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 890151445 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 890151445 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1886554389 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1886554389 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 844 # Number of read requests accepted
+system.mem_ctrls.writeReqs 754 # Number of write requests accepted
+system.mem_ctrls.readBursts 844 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 754 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 7296 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 42112 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 54016 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 48256 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 77 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 227 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 250 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 208 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 219 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 42 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
+system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
+system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
+system.mem_ctrls.totGap 54170 # Total gap between requests
+system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 844 # Read request sizes (log2)
+system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
+system.mem_ctrls.writePktSize::6 754 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 587 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 140 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
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+system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::15 21 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 37 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.mem_ctrls.bytesPerActivate::samples 97 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 888.742268 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 795.135498 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 283.200947 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 8 8.25% 8.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 2 2.06% 10.31% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 3 3.09% 13.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2 2.06% 15.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 4.12% 19.59% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1 1.03% 20.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 2 2.06% 22.68% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 75 77.32% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 97 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 19.052632 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 18.749953 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 3.938359 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 2 5.26% 5.26% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 13 34.21% 39.47% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 9 23.68% 63.16% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-21 8 21.05% 84.21% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::22-23 4 10.53% 94.74% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-25 1 2.63% 97.37% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::38-39 1 2.63% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17.315789 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 17.271887 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.254296 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 16 42.11% 42.11% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 2 5.26% 47.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 13 34.21% 81.58% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 6 15.79% 97.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 1 2.63% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 6080 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 19950 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 8.33 # Average queueing delay per DRAM burst
+system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
+system.mem_ctrls.avgMemAccLat 27.33 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 861.82 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 776.82 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 996.40 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 890.15 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.mem_ctrls.busUtil 12.80 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 6.73 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 6.07 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 1.34 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 24.81 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 637 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 650 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 87.26 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 96.01 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 33.90 # Average gap between requests
+system.mem_ctrls.pageHitRate 91.47 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 650160 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 361200 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7725120 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 5723136 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 32013252 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 103800 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 49628028 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 1056.454956 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 45411 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 1009584 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 27291600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 31352544 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 667.615178 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 45416 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.outstanding_req_hist_seqr::bucket_size 2
+system.ruby.outstanding_req_hist_seqr::max_bucket 19
+system.ruby.outstanding_req_hist_seqr::samples 985
+system.ruby.outstanding_req_hist_seqr::mean 15.747208
+system.ruby.outstanding_req_hist_seqr::gmean 15.641156
+system.ruby.outstanding_req_hist_seqr::stdev 1.199617
+system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.41% 1.12% | 2 0.20% 1.32% | 3 0.30% 1.62% | 110 11.17% 12.79% | 859 87.21% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 985
+system.ruby.latency_hist_seqr::bucket_size 256
+system.ruby.latency_hist_seqr::max_bucket 2559
+system.ruby.latency_hist_seqr::samples 970
+system.ruby.latency_hist_seqr::mean 876.382474
+system.ruby.latency_hist_seqr::gmean 454.463576
+system.ruby.latency_hist_seqr::stdev 370.932806
+system.ruby.latency_hist_seqr | 146 15.05% 15.05% | 6 0.62% 15.67% | 4 0.41% 16.08% | 388 40.00% 56.08% | 418 43.09% 99.18% | 8 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 970
+system.ruby.hit_latency_hist_seqr::bucket_size 1
+system.ruby.hit_latency_hist_seqr::max_bucket 9
+system.ruby.hit_latency_hist_seqr::samples 92
+system.ruby.hit_latency_hist_seqr::mean 1
+system.ruby.hit_latency_hist_seqr::gmean 1
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.miss_latency_hist_seqr::bucket_size 256
+system.ruby.miss_latency_hist_seqr::max_bucket 2559
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+system.ruby.miss_latency_hist_seqr::gmean 862.901849
+system.ruby.miss_latency_hist_seqr::stdev 251.425992
+system.ruby.miss_latency_hist_seqr | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 878
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 44 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
+system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 75 # Number of times a store aliased with a pending store
+system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store
+system.ruby.l2_cntrl0.L2cache.demand_hits 36 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 844 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 880 # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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+system.ruby.LD.latency_hist_seqr::bucket_size 128
+system.ruby.LD.latency_hist_seqr::max_bucket 1279
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+system.ruby.LD.latency_hist_seqr::gmean 437.265598
+system.ruby.LD.latency_hist_seqr::stdev 350.325488
+system.ruby.LD.latency_hist_seqr | 7 12.96% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 5 9.26% 22.22% | 29 53.70% 75.93% | 9 16.67% 92.59% | 4 7.41% 100.00%
+system.ruby.LD.latency_hist_seqr::total 54
+system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
+system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
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+system.ruby.LD.hit_latency_hist_seqr::mean 1
+system.ruby.LD.hit_latency_hist_seqr::gmean 1
+system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 6
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
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+system.ruby.LD.miss_latency_hist_seqr::stdev 169.695753
+system.ruby.LD.miss_latency_hist_seqr | 1 2.08% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 5 10.42% 12.50% | 29 60.42% 72.92% | 9 18.75% 91.67% | 4 8.33% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 48
+system.ruby.ST.latency_hist_seqr::bucket_size 256
+system.ruby.ST.latency_hist_seqr::max_bucket 2559
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+system.ruby.ST.latency_hist_seqr::gmean 509.527867
+system.ruby.ST.latency_hist_seqr::stdev 331.108106
+system.ruby.ST.latency_hist_seqr | 93 10.69% 10.69% | 6 0.69% 11.38% | 4 0.46% 11.84% | 354 40.69% 52.53% | 405 46.55% 99.08% | 8 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::total 870
+system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
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+system.ruby.ST.hit_latency_hist_seqr::mean 1
+system.ruby.ST.hit_latency_hist_seqr::gmean 1
+system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist_seqr::total 84
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 256
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+system.ruby.ST.miss_latency_hist_seqr::stdev 146.709443
+system.ruby.ST.miss_latency_hist_seqr | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 354 45.04% 47.46% | 405 51.53% 98.98% | 8 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::total 786
+system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
+system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
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+system.ruby.IFETCH.latency_hist_seqr::stdev 37.753363
+system.ruby.IFETCH.latency_hist_seqr | 4 8.70% 8.70% | 14 30.43% 39.13% | 21 45.65% 84.78% | 1 2.17% 86.96% | 4 8.70% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
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+system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
+system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 2
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+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.479403
+system.ruby.IFETCH.miss_latency_hist_seqr | 2 4.55% 4.55% | 14 31.82% 36.36% | 21 47.73% 84.09% | 1 2.27% 86.36% | 4 9.09% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total 44
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+system.ruby.Directory_Controller.GETS 83 0.00% 0.00%
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+system.ruby.Directory_Controller.Unblock 77 0.00% 0.00%
+system.ruby.Directory_Controller.Last_Unblock 5 0.00% 0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock 760 0.00% 0.00%
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+system.ruby.Directory_Controller.Memory_Ack 754 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 691 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00%
+system.ruby.Directory_Controller.I.Memory_Ack 754 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETX 70 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETS 5 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 755 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock 5 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Memory_Data 5 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Memory_Data 760 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback 754 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 56 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 59 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 880 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 80012 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 83 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 874 0.00% 0.00%
+system.ruby.L1Cache_Controller.All_acks 786 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_Timeout 795 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 48 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 44 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 788 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 81 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 7 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 68 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 787 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Load 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 15 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30902 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout 786 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement 45597 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data 786 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement 45 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.All_acks 786 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement 2588 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 83 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 9 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 81 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Ifetch 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Store 8 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 92 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 788 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 794 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 843 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 754 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 795 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 836 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 761 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 794 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 755 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 81 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 793 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 83 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 82 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 760 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 26 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 754 0.00% 0.00%
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff