Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern

[yosys.git] / tests / rpc / frontend.py

diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py
index eace07bf91c0ba682f139b6eafde27663b62c23b..8cbec568238a7937720b603cad3d92f373530f50 100644 (file)
--- a/tests/rpc/frontend.py
+++ b/tests/rpc/frontend.py
@@ -83,10 +83,11 @@ def main():
 
        if args.mode == "unix-socket":
                sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
+               sock.settimeout(30)
                sock.bind(args.path)
                try:
-                       ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
                        sock.listen(1)
+                       ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
                        conn, addr = sock.accept()
                        file = conn.makefile("rw")
                        while True: