verific: Fix conditions of SVAs with explicit clocks within procedures

[yosys.git] / tests / sva / nested_clk_else.sv

diff --git a/tests/sva/nested_clk_else.sv b/tests/sva/nested_clk_else.sv
new file mode 100644 (file)
index 0000000..4421cb3
--- /dev/null
+++ b/tests/sva/nested_clk_else.sv
@@ -0,0 +1,11 @@
+module top (input clk, a, b);
+       always @(posedge clk) begin
+        if (a);
+        else assume property (@(posedge clk) b);
+       end
+
+`ifndef FAIL
+    assume property (@(posedge clk) !a);
+`endif
+    assert property (@(posedge clk) b);
+endmodule