Fix wire width

[yosys.git] / tests / various / abc9.v

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index a08b613a8ce6c694a9ad7a03a3bbccfa08a84c34..30ebd4e26c9fb410c5f6bcd9c235fab64efa17dd 100644 (file)
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -5,5 +5,7 @@ always @*
 endmodule
 
 module abc9_test028(input i, output o);
-unknown u(~i, o);
+wire w;
+unknown u(~i, w);
+unknown2 u2(w, o);
 endmodule