cpt.set(new_sec, 'bootUncacheability', 'false')
cpt.set(new_sec, 'num_entries', '0')
+# Version 10 adds block_size_bytes to system.ruby
+def from_9(cpt):
+ for sec in cpt.sections():
+ if sec == 'system.ruby':
+ # Use Gem5's default of 64; this should be changed if the to be
+ # upgraded checkpoints were not taken with block-size 64!
+ cpt.set(sec, 'block_size_bytes', '64')
+
+# Checkpoint version 11 (0xB) adds the perfLevel variable in the clock domain
+# and voltage domain simObjects used for DVFS and is serialized and
+# unserialized.
+def from_A(cpt):
+ for sec in cpt.sections():
+ import re
+
+ if re.match('^.*sys.*[._]clk_domain$', sec):
+ # Make _perfLevel equal to 0 which means best performance
+ cpt.set(sec, '_perfLevel', ' '.join('0'))
+ elif re.match('^.*sys.*[._]voltage_domain$', sec):
+ # Make _perfLevel equal to 0 which means best performance
+ cpt.set(sec, '_perfLevel', ' '.join('0'))
+ else:
+ continue
+
+# The change between versions C and D is the addition of support for multiple
+# event queues, so for old checkpoints we must specify that there's only one.
+def from_B(cpt):
+ cpt.set('Globals', 'numMainEventQueues', '1')
+
+# Checkpoint version D uses condition code registers for the ARM
+# architecture; previously the integer register file was used for these
+# registers. To upgrade, we move those 5 integer registers to the ccRegs
+# register file.
+def from_C(cpt):
+ if cpt.get('root','isa') == 'arm':
+ for sec in cpt.sections():
+ import re
+
+ re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
+ # Search for all the execution contexts
+ if not re_cpu_match:
+ continue
+
+ items = []
+ for (item,value) in cpt.items(sec):
+ items.append(item)
+ if 'ccRegs' not in items:
+ intRegs = cpt.get(sec, 'intRegs').split()
+
+ ccRegs = intRegs[38:43]
+ del intRegs[38:43]
+
+ ccRegs.append('0') # CCREG_ZERO
+
+ cpt.set(sec, 'intRegs', ' '.join(intRegs))
+ cpt.set(sec, 'ccRegs', ' '.join(ccRegs))
migrations = []
migrations.append(from_0)
migrations.append(from_6)
migrations.append(from_7)
migrations.append(from_8)
+migrations.append(from_9)
+migrations.append(from_A)
+migrations.append(from_B)
+migrations.append(from_C)
verbose_print = False