attempting to get libre-soc boot on ulx3s-85f

[libresoc-litex.git] / versa_ecp5.py

diff --git a/versa_ecp5.py b/versa_ecp5.py
index a3772e793b3f6c2bb5c7afd5a11229e4479b7f3b..42ff88f24b2bf4c7d766547f4c83439508a31f32 100755 (executable)
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -84,6 +84,7 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
         kwargs["l2_size"] = 0
         #bus_data_width = 16,
 
@@ -126,9 +127,9 @@ class ArtyTestSoC(arty.BaseSoC):
         arty.BaseSoC.__init__(self,
             sys_clk_freq = sys_clk_freq,
             cpu_type     = "external",
-            #cpu_cls      = LibreSoC,
-            #cpu_variant  = "standardjtag",
-            cpu_cls      = Microwatt,
+            cpu_cls      = LibreSoC,
+            cpu_variant  = "standardjtag",
+            #cpu_cls      = Microwatt,
             variant      = "a7-100",
             toolchain    = "symbiflow",
             **kwargs)
@@ -160,7 +161,6 @@ def main():
                                **soc_sdram_argdict(args))
 
     elif args.fpga == "ulx3s85f":
-        trellis_args(parser)
         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                               **soc_sdram_argdict(args))