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[libreriscv.git] / why_a_libresoc.mdwn

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@@ -1,6 +1,6 @@
-## Why a Libre SOC?
+## Why a Libre-SOC?
 
-Its quite hard to guarantee that a performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
+Its quite hard to guarantee that performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
 
 There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution).
 
@@ -8,14 +8,14 @@ Given the fact that performant bug-free processors no longer exist, how can you
 
 *Collaboration, not competition*.
 
-Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC.
+Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire Libre-SOC.
 
 ## Benefits: Privacy, Safety-Critical, Peace of Mind...
 
-Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
+Our Libre-SOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
 
 There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...).
-LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access
+Libre-SOC posits that it is impossible to trust a processor in a safety critical environment without both access
 to that processor's source, a cycle accurate HDL simulator that guarantees developers their code behaves as they 
 expect, and formal correctness proofs. An ISA level simulator is no longer satisfactory.