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@@ -4,16 +4,19 @@ Its quite hard to guarantee that a performant processors (think pipelined, out-o
 
 There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution).
 
-Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
+Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study, improve them, run the test suites and be able to improve those too.  Not only that, you and everyone who has a stake in the success needs to be entirely free from NDAs and other restrictions which prevent and prohibit communication.
+
+*Collaboration, not competition*.
 
 Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC.
 
 ## Benefits: Privacy, Safety-Critical, Peace of Mind...
+
 Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
 
 There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...).
 LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access
-to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they 
-expect. An ISA level simulator is no longer satisfactory.
+to that processor's source, a cycle accurate HDL simulator that guarantees developers their code behaves as they 
+expect, and formal correctness proofs. An ISA level simulator is no longer satisfactory.
 
 Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.