wishbone_bram_wrapper ram_addr_bits is 1 bit off

[microwatt.git] / wishbone_bram_wrapper.vhdl

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index 182fd29d745c1eb0b1943334204056ce949a48ff..a45790fe55ac0255af09ea2452f175e9f5aef681 100644 (file)
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;
 
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;
 
     -- RAM interface
     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);