Give exceptions a separate path to writeback

[microwatt.git] / wishbone_debug_master.vhdl

diff --git a/wishbone_debug_master.vhdl b/wishbone_debug_master.vhdl
index b8d936ba622848b87256a258c8607340f9b02929..11b9ee3d731354c5001aec2c60ba648e5210b82f 100644 (file)
--- a/wishbone_debug_master.vhdl
+++ b/wishbone_debug_master.vhdl
@@ -117,14 +117,13 @@ begin
     dmi_ack <= dmi_req when (dmi_addr /= DBG_WB_DATA or state = DMI_WAIT) else '0';
 
        -- Some WB signals are direct wires from registers or DMI
-    wb_out.adr <= reg_addr;
+    wb_out.adr <= reg_addr(wb_out.adr'left downto 0);
     wb_out.dat <= dmi_din;
     wb_out.sel <= reg_ctrl(7 downto 0);
     wb_out.we  <= dmi_wr;
 
     -- We always move WB cyc and stb simultaneously (no pipelining yet...)
     wb_out.cyc <= '1' when state = WB_CYCLE else '0';
-    wb_out.stb <= '1' when state = WB_CYCLE else '0';
 
     -- Data latch. WB will take the read data away as soon as the cycle
     -- terminates but we must maintain it on DMI until req goes down, so
@@ -145,14 +144,23 @@ begin
        if rising_edge(clk) then
            if (rst) then
                state <= IDLE;
+               wb_out.stb <= '0';
            else
                case state is
                when IDLE =>
                    if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
                        state <= WB_CYCLE;
+                       wb_out.stb <= '1';
                    end if;
                when WB_CYCLE =>
+                   if wb_in.stall = '0' then
+                       wb_out.stb <= '0';
+                   end if;
                    if wb_in.ack then
+                       -- We shouldn't get the ack if we hadn't already cleared
+                       -- stb above but if this happen, don't leave it dangling.
+                       --
+                       wb_out.stb <= '0';
                        state <= DMI_WAIT;
                    end if;
                when DMI_WAIT =>