Add Tercel PHY reset synchronization

[microwatt.git] / wishbone_debug_master.vhdl

diff --git a/wishbone_debug_master.vhdl b/wishbone_debug_master.vhdl
index 3ba6b21518fe638e5bf9622e4d98c415be6b2771..ddf692386c1493694e60a4939ded03e2e68fdf2c 100644 (file)
--- a/wishbone_debug_master.vhdl
+++ b/wishbone_debug_master.vhdl
@@ -49,6 +49,7 @@ architecture behaviour of wishbone_debug_master is
     
     type state_t is (IDLE, WB_CYCLE, DMI_WAIT);
     signal state : state_t;
+    signal do_inc : std_ulogic;
 
 begin
 
@@ -84,16 +85,16 @@ begin
                reg_addr <= (others => '0');
                reg_ctrl <= (others => '0');
            else            -- Standard register writes
-               if dmi_req and dmi_wr then
+                if do_inc = '1' then
+                   -- Address register auto-increment
+                   reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
+                                                 decode_autoinc(reg_ctrl(10 downto 9)));
+                elsif dmi_req and dmi_wr then
                    if dmi_addr = DBG_WB_ADDR then
                        reg_addr <= dmi_din;
                    elsif dmi_addr = DBG_WB_CTRL then
                        reg_ctrl <= dmi_din(10 downto 0);
                    end if;
-                elsif state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1'  then
-                   -- Address register auto-increment
-                   reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
-                                                 decode_autoinc(reg_ctrl(10 downto 9)));
                end if;
            end if;
        end if;
@@ -124,7 +125,6 @@ begin
 
     -- We always move WB cyc and stb simultaneously (no pipelining yet...)
     wb_out.cyc <= '1' when state = WB_CYCLE else '0';
-    wb_out.stb <= '1' when state = WB_CYCLE else '0';
 
     -- Data latch. WB will take the read data away as soon as the cycle
     -- terminates but we must maintain it on DMI until req goes down, so
@@ -145,20 +145,32 @@ begin
        if rising_edge(clk) then
            if (rst) then
                state <= IDLE;
+               wb_out.stb <= '0';
+                do_inc <= '0';
            else
                case state is
                when IDLE =>
                    if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
                        state <= WB_CYCLE;
+                       wb_out.stb <= '1';
                    end if;
                when WB_CYCLE =>
+                   if wb_in.stall = '0' then
+                       wb_out.stb <= '0';
+                   end if;
                    if wb_in.ack then
+                       -- We shouldn't get the ack if we hadn't already cleared
+                       -- stb above but if this happen, don't leave it dangling.
+                       --
+                       wb_out.stb <= '0';
                        state <= DMI_WAIT;
+                        do_inc <= reg_ctrl(8);
                    end if;
                when DMI_WAIT =>
                    if dmi_req = '0' then
                        state <= IDLE;
                    end if;
+                    do_inc <= '0';
                end case;
            end if;
        end if;