* <https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html>
* Discussion: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002342.html>
* [[rv_major_opcode_1010011]] for opcode listing.
+* [[zfpacc_proposal]] for accuracy settings proposal
Extension subsets:
# TODO:
-* Decision on accuracy
+* Decision on accuracy, moved to [[zfpacc_proposal]]
<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002355.html>
* Errors **MUST** be repeatable.
-* How about three Platform Specifications? 3D, UNIX and Embedded?
+* How about four Platform Specifications? 3DUNIX, UNIX, 3DEmbedded and Embedded?
<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002361.html>
Accuracy requirements for dual (triple) purpose implementations must
meet the higher standard.
* Reciprocal Square-root is in its own separate extension (Zfrsqrt) as
it is desirable on its own by other implementors. This to be evaluated.
+# Proposed Opcodes vs Khronos OpenCL Opcodes <a name="khronos_equiv"></a>
+
+This list shows the (direct) equivalence between proposed opcodes and
+their Khronos OpenCL equivalents.
+
+See
+<https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html>
+
+Special FP16 opcodes are *not* being proposed, except by indirect / inherent
+use of the "fmt" field that is already present in the RISC-V Specification.
+
+"Native" opcodes are *not* being proposed: implementors will be expected
+to use the (equivalent) proposed opcode covering the same function.
+
+"Fast" opcodes are *not* being proposed, because the Khronos Specification
+fast\_length, fast\_normalise and fast\_distance OpenCL opcodes require
+vectors (or can be done as scalar operations using other RISC-V instructions).
+
+The OpenCL FP32 opcodes are **direct** equivalents to the proposed opcodes.
+Deviation from conformance with the Khronos Specification - including the
+Khronos Specification accuracy requirements - is not an option.
+
+[[!table data="""
+Proposed opcode | OpenCL FP32 | OpenCL FP16 | OpenCL native | OpenCL fast |
+FSIN | sin | half\_sin | native\_sin | NONE |
+FCOS | cos | half\_cos | native\_cos | NONE |
+FTAN | tan | half\_tan | native\_tan | NONE |
+FASIN | asin | NONE | NONE | NONE |
+FACOS | acos | NONE | NONE | NONE |
+FSINPI | sinpi | NONE | NONE | NONE |
+FCOSPI | cospi | NONE | NONE | NONE |
+FTANPI | tanpi | NONE | NONE | NONE |
+FASINPI | asinpi | NONE | NONE | NONE |
+FACOSPI | acospi | NONE | NONE | NONE |
+FATANPI | atanpi | NONE | NONE | NONE |
+FSINH | sinh | NONE | NONE | NONE |
+FCOSH | cosh | NONE | NONE | NONE |
+FTANH | tanh | NONE | NONE | NONE |
+FASINH | asinh | NONE | NONE | NONE |
+FACOSH | acosh | NONE | NONE | NONE |
+FATANH | atanh | NONE | NONE | NONE |
+FRSQRT | rsqrt | half\_rsqrt | native\_rsqrt | NONE |
+FCBRT | cbrt | NONE | NONE | NONE |
+FEXP2 | exp2 | half\_exp2 | native\_exp2 | NONE |
+FLOG2 | log2 | half\_log2 | native\_log2 | NONE |
+FEXPM1 (1) | expm1 | NONE | NONE | NONE |
+FLOG1P (1) | log1p | NONE | NONE | NONE |
+FEXP (1) | exp | half\_exp | native\_exp | NONE |
+FLOG (1) | log | half\_log | native\_log | NONE |
+FEXP10 | exp10 | half\_exp10 | native\_exp10 | NONE |
+FLOG10 | log10 | half\_log10 | native\_log10 | NONE |
+FATAN2 | atan2 | NONE | NONE | NONE |
+FATAN2PI | atan2pi | NONE | NONE | NONE |
+FPOW | pow | NONE | NONE | NONE |
+FROOT | rootn | NONE | NONE | NONE |
+FHYPOT | hypot | NONE | NONE | NONE |
+"""]]
+
+Note (1): See "synthesis", below. FEXPM1, FEXP and FLOG1P, FLOG, may
+be synthesised in terms of the other. FEXPM1 and FLOG1P are more accurate.
+It is likely therefore that FLOG and FEXP will be removed.
# List of 2-arg opcodes
Research needed to ensure that implementors are not compromised by such
a decision
<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002358.html>
+
projects / libreriscv.git / blobdiff