X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=inline;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=3c50471c63b88c902b55d06ab482d323e36896c7;hb=b4477fa4d46345d1e8742c1d57c9dcc432edaf51;hp=d53a500fe61e5d77cb0e97a185e0a4c1b5d82a98;hpb=f2b3e96e754a5d722f2b0fa1bd5efa1c0640ed3b;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index d53a500fe61..3c50471c63b 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -30,6 +30,7 @@ #include "radv_debug.h" #include "radv_private.h" #include "radv_shader.h" +#include "radv_shader_helper.h" #include "nir/nir.h" #include "nir/nir_builder.h" #include "spirv/nir_spirv.h" @@ -39,7 +40,6 @@ #include #include "sid.h" -#include "gfx9d.h" #include "ac_binary.h" #include "ac_llvm_util.h" #include "ac_nir_to_llvm.h" @@ -52,11 +52,14 @@ static const struct nir_shader_compiler_options nir_options = { .vertex_id_zero_based = true, .lower_scmp = true, + .lower_flrp16 = true, .lower_flrp32 = true, .lower_flrp64 = true, .lower_device_index_to_zero = true, .lower_fsat = true, .lower_fdiv = true, + .lower_bitfield_insert_to_bitfield_select = true, + .lower_bitfield_extract = true, .lower_sub = true, .lower_pack_snorm_2x16 = true, .lower_pack_snorm_4x8 = true, @@ -70,7 +73,7 @@ static const struct nir_shader_compiler_options nir_options = { .lower_extract_word = true, .lower_ffma = true, .lower_fpow = true, - .vs_inputs_dual_locations = true, + .lower_mul_2x32_64 = true, .max_unroll_iterations = 32 }; @@ -118,16 +121,37 @@ void radv_DestroyShaderModule( } void -radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively) +radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, + bool allow_copies) { bool progress; + unsigned lower_flrp = + (shader->options->lower_flrp16 ? 16 : 0) | + (shader->options->lower_flrp32 ? 32 : 0) | + (shader->options->lower_flrp64 ? 64 : 0); do { progress = false; + NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp); + NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp); + NIR_PASS_V(shader, nir_lower_vars_to_ssa); NIR_PASS_V(shader, nir_lower_pack); - NIR_PASS_V(shader, nir_lower_alu_to_scalar); + + if (allow_copies) { + /* Only run this pass in the first call to + * radv_optimize_nir. Later calls assume that we've + * lowered away any copy_deref instructions and we + * don't want to introduce any more. + */ + NIR_PASS(progress, shader, nir_opt_find_array_copies); + } + + NIR_PASS(progress, shader, nir_opt_copy_prop_vars); + NIR_PASS(progress, shader, nir_opt_dead_write_vars); + + NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL); NIR_PASS_V(shader, nir_lower_phis_to_scalar); NIR_PASS(progress, shader, nir_copy_prop); @@ -139,12 +163,33 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively) NIR_PASS(progress, shader, nir_opt_remove_phis); NIR_PASS(progress, shader, nir_opt_dce); } - NIR_PASS(progress, shader, nir_opt_if); + NIR_PASS(progress, shader, nir_opt_if, true); NIR_PASS(progress, shader, nir_opt_dead_cf); NIR_PASS(progress, shader, nir_opt_cse); - NIR_PASS(progress, shader, nir_opt_peephole_select, 8); - NIR_PASS(progress, shader, nir_opt_algebraic); + NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true); NIR_PASS(progress, shader, nir_opt_constant_folding); + NIR_PASS(progress, shader, nir_opt_algebraic); + + if (lower_flrp != 0) { + bool lower_flrp_progress = false; + NIR_PASS(lower_flrp_progress, + shader, + nir_lower_flrp, + lower_flrp, + false /* always_precise */, + shader->options->lower_ffma); + if (lower_flrp_progress) { + NIR_PASS(progress, shader, + nir_opt_constant_folding); + progress = true; + } + + /* Nothing should rematerialize any flrps, so we only + * need to do this lowering once. + */ + lower_flrp = 0; + } + NIR_PASS(progress, shader, nir_opt_undef); NIR_PASS(progress, shader, nir_opt_conditional_discard); if (shader->options->max_unroll_iterations) { @@ -162,21 +207,19 @@ radv_shader_compile_to_nir(struct radv_device *device, const char *entrypoint_name, gl_shader_stage stage, const VkSpecializationInfo *spec_info, - const VkPipelineCreateFlags flags) + const VkPipelineCreateFlags flags, + const struct radv_pipeline_layout *layout) { nir_shader *nir; - nir_function *entry_point; if (module->nir) { /* Some things such as our meta clear/blit code will give us a NIR * shader directly. In that case, we just ignore the SPIR-V entirely * and just use the NIR shader */ nir = module->nir; nir->options = &nir_options; - nir_validate_shader(nir); + nir_validate_shader(nir, "in internal shader"); assert(exec_list_length(&nir->functions) == 1); - struct exec_node *node = exec_list_get_head(&nir->functions); - entry_point = exec_node_data(nir_function, node, node); } else { uint32_t *spirv = (uint32_t *) module->data; assert(module->size % 4 == 0); @@ -202,36 +245,56 @@ radv_shader_compile_to_nir(struct radv_device *device, } } const struct spirv_to_nir_options spirv_options = { + .lower_ubo_ssbo_access_to_offsets = true, .caps = { + .amd_gcn_shader = true, + .amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT, + .amd_trinary_minmax = true, + .derivative_group = true, + .descriptor_array_dynamic_indexing = true, + .descriptor_array_non_uniform_indexing = true, + .descriptor_indexing = true, .device_group = true, .draw_parameters = true, + .float16 = true, .float64 = true, + .geometry_streams = true, .image_read_without_format = true, .image_write_without_format = true, - .tessellation = true, + .int8 = true, + .int16 = true, .int64 = true, + .int64_atomics = true, .multiview = true, + .physical_storage_buffer_address = true, + .runtime_descriptor_array = true, + .shader_viewport_index_layer = true, + .stencil_export = true, + .storage_8bit = true, + .storage_16bit = true, + .storage_image_ms = true, + .subgroup_arithmetic = true, .subgroup_ballot = true, .subgroup_basic = true, .subgroup_quad = true, .subgroup_shuffle = true, .subgroup_vote = true, + .tessellation = true, + .transform_feedback = true, .variable_pointers = true, - .gcn_shader = true, - .trinary_minmax = true, - .shader_viewport_index_layer = true, - .descriptor_array_dynamic_indexing = true, - .runtime_descriptor_array = true, - .stencil_export = true, }, + .ubo_addr_format = nir_address_format_32bit_index_offset, + .ssbo_addr_format = nir_address_format_32bit_index_offset, + .phys_ssbo_addr_format = nir_address_format_64bit_global, + .push_const_addr_format = nir_address_format_logical, + .shared_addr_format = nir_address_format_32bit_offset, }; - entry_point = spirv_to_nir(spirv, module->size / 4, - spec_entries, num_spec_entries, - stage, entrypoint_name, - &spirv_options, &nir_options); - nir = entry_point->shader; + nir = spirv_to_nir(spirv, module->size / 4, + spec_entries, num_spec_entries, + stage, entrypoint_name, + &spirv_options, &nir_options); assert(nir->info.stage == stage); - nir_validate_shader(nir); + nir_validate_shader(nir, "after spirv_to_nir"); free(spec_entries); @@ -239,27 +302,25 @@ radv_shader_compile_to_nir(struct radv_device *device, * inline functions. That way they get properly initialized at the top * of the function and not at the top of its caller. */ - NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local); + NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp); NIR_PASS_V(nir, nir_lower_returns); NIR_PASS_V(nir, nir_inline_functions); - NIR_PASS_V(nir, nir_copy_prop); + NIR_PASS_V(nir, nir_opt_deref); /* Pick off the single entrypoint that we want */ foreach_list_typed_safe(nir_function, func, node, &nir->functions) { - if (func != entry_point) + if (func->is_entrypoint) + func->name = ralloc_strdup(func, "main"); + else exec_node_remove(&func->node); } assert(exec_list_length(&nir->functions) == 1); - entry_point->name = ralloc_strdup(entry_point, "main"); /* Make sure we lower constant initializers on output variables so that * nir_remove_dead_variables below sees the corresponding stores */ NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out); - NIR_PASS_V(nir, nir_remove_dead_variables, - nir_var_shader_in | nir_var_shader_out | nir_var_system_value); - /* Now that we've deleted all but the main function, we can go ahead and * lower the rest of the constant initializers. */ @@ -271,17 +332,22 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_split_per_member_structs); + NIR_PASS_V(nir, nir_remove_dead_variables, + nir_var_shader_in | nir_var_shader_out | nir_var_system_value); + NIR_PASS_V(nir, nir_lower_system_values); NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays); + NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout); } /* Vulkan uses the separate-shader linking model */ nir->info.separate_shader = true; - nir_shader_gather_info(nir, entry_point->impl); + nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); static const nir_lower_tex_options tex_options = { .lower_txp = ~0, + .lower_tg4_offsets = true, }; nir_lower_tex(nir, &tex_options); @@ -299,10 +365,9 @@ radv_shader_compile_to_nir(struct radv_device *device, } nir_split_var_copies(nir); - nir_lower_var_copies(nir); nir_lower_global_vars_to_local(nir); - nir_remove_dead_variables(nir, nir_var_local); + nir_remove_dead_variables(nir, nir_var_function_temp); nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { .subgroup_size = 64, .ballot_bit_size = 64, @@ -313,8 +378,15 @@ radv_shader_compile_to_nir(struct radv_device *device, .lower_vote_eq_to_ballot = 1, }); + nir_lower_load_const_to_scalar(nir); + if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) - radv_optimize_nir(nir, false); + radv_optimize_nir(nir, false, true); + + /* We call nir_lower_var_copies() after the first radv_optimize_nir() + * to remove any copies introduced by nir_opt_find_array_copies(). + */ + nir_lower_var_copies(nir); /* Indirect lowering must be called after the radv_optimize_nir() loop * has been called at least once. Otherwise indirect lowering can @@ -322,7 +394,7 @@ radv_shader_compile_to_nir(struct radv_device *device, * considered too large for unrolling. */ ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class); - radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT); + radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false); return nir; } @@ -360,8 +432,9 @@ radv_alloc_shader_memory(struct radv_device *device, slab->bo = device->ws->buffer_create(device->ws, slab->size, 256, RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING | - device->physical_device->cpdma_prefetch_writes_memory ? - 0 : RADEON_FLAG_READ_ONLY); + (device->physical_device->cpdma_prefetch_writes_memory ? + 0 : RADEON_FLAG_READ_ONLY), + RADV_BO_PRIORITY_SHADER); slab->ptr = (char*)device->ws->buffer_map(slab->bo); list_inithead(&slab->shaders); @@ -398,6 +471,7 @@ radv_get_shader_binary_size(struct ac_shader_binary *binary) static void radv_fill_shader_variant(struct radv_device *device, struct radv_shader_variant *variant, + struct radv_nir_compiler_options *options, struct ac_shader_binary *binary, gl_shader_stage stage) { @@ -407,7 +481,13 @@ radv_fill_shader_variant(struct radv_device *device, variant->code_size = radv_get_shader_binary_size(binary); variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | - S_00B12C_SCRATCH_EN(scratch_enabled); + S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) | + S_00B12C_SCRATCH_EN(scratch_enabled) | + S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | + S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) | + S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) | + S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) | + S_00B12C_SO_EN(!!info->so.num_outputs); variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | @@ -416,7 +496,13 @@ radv_fill_shader_variant(struct radv_device *device, switch (stage) { case MESA_SHADER_TESS_EVAL: - vgpr_comp_cnt = 3; + if (options->key.tes.as_es) { + assert(device->physical_device->rad_info.chip_class <= GFX8); + vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; + } else { + bool enable_prim_id = options->key.tes.export_prim_id || info->uses_prim_id; + vgpr_comp_cnt = enable_prim_id ? 3 : 2; + } variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); break; case MESA_SHADER_TESS_CTRL: @@ -455,7 +541,7 @@ radv_fill_shader_variant(struct radv_device *device, if (es_type == MESA_SHADER_VERTEX) { es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; } else if (es_type == MESA_SHADER_TESS_EVAL) { - es_vgpr_comp_cnt = 3; + es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; } else { unreachable("invalid shader ES type"); } @@ -514,9 +600,15 @@ static void radv_init_llvm_target() * * "mesa" is the prefix for error messages. */ - const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false", - "-amdgpu-skip-threshold=1" }; - LLVMParseCommandLineOptions(3, argv, NULL); + if (HAVE_LLVM >= 0x0800) { + const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" }; + LLVMParseCommandLineOptions(2, argv, NULL); + + } else { + const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false", + "-amdgpu-skip-threshold=1" }; + LLVMParseCommandLineOptions(3, argv, NULL); + } } static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT; @@ -541,8 +633,8 @@ shader_variant_create(struct radv_device *device, enum ac_target_machine_options tm_options = 0; struct radv_shader_variant *variant; struct ac_shader_binary binary; - LLVMTargetMachineRef tm; - + struct ac_llvm_compiler ac_llvm; + bool thread_compiler; variant = calloc(1, sizeof(struct radv_shader_variant)); if (!variant) return NULL; @@ -561,27 +653,34 @@ shader_variant_create(struct radv_device *device, tm_options |= AC_TM_SUPPORTS_SPILL; if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) tm_options |= AC_TM_SISCHED; + if (options->check_ir) + tm_options |= AC_TM_CHECK_IR; + if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT) + tm_options |= AC_TM_NO_LOAD_STORE_OPT; + thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM); radv_init_llvm_once(); - tm = ac_create_target_machine(chip_family, tm_options, NULL); + radv_init_llvm_compiler(&ac_llvm, + thread_compiler, + chip_family, tm_options); if (gs_copy_shader) { assert(shader_count == 1); - radv_compile_gs_copy_shader(tm, *shaders, &binary, + radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary, &variant->config, &variant->info, options); } else { - radv_compile_nir_shader(tm, &binary, &variant->config, + radv_compile_nir_shader(&ac_llvm, &binary, &variant->config, &variant->info, shaders, shader_count, options); } - LLVMDisposeTargetMachine(tm); + radv_destroy_llvm_compiler(&ac_llvm, thread_compiler); - radv_fill_shader_variant(device, variant, &binary, stage); + radv_fill_shader_variant(device, variant, options, &binary, stage); if (code_out) { *code_out = binary.code; - *code_size_out = variant->code_size; + *code_size_out = binary.code_size; } else free(binary.code); free(binary.config); @@ -681,7 +780,8 @@ generate_shader_stats(struct radv_device *device, gl_shader_stage stage, struct _mesa_string_buffer *buf) { - unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; + enum chip_class chip_class = device->physical_device->rad_info.chip_class; + unsigned lds_increment = chip_class >= GFX7 ? 512 : 256; struct ac_shader_config *conf; unsigned max_simd_waves; unsigned lds_per_wave = 0; @@ -694,12 +794,17 @@ generate_shader_stats(struct radv_device *device, lds_per_wave = conf->lds_size * lds_increment + align(variant->info.fs.num_interp * 48, lds_increment); + } else if (stage == MESA_SHADER_COMPUTE) { + unsigned max_workgroup_size = + radv_nir_get_max_workgroup_size(chip_class, variant->nir); + lds_per_wave = (conf->lds_size * lds_increment) / + DIV_ROUND_UP(max_workgroup_size, 64); } if (conf->num_sgprs) max_simd_waves = MIN2(max_simd_waves, - radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs); + ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs); if (conf->num_vgprs) max_simd_waves = @@ -778,13 +883,13 @@ radv_GetShaderInfoAMD(VkDevice _device, if (!pInfo) { *pInfoSize = sizeof(VkShaderStatisticsInfoAMD); } else { - unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; + unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256; struct ac_shader_config *conf = &variant->config; VkShaderStatisticsInfoAMD statistics = {}; statistics.shaderStageMask = shaderStage; statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS; - statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device); + statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class); statistics.numAvailableSgprs = statistics.numPhysicalSgprs; if (stage == MESA_SHADER_COMPUTE) { @@ -821,6 +926,7 @@ radv_GetShaderInfoAMD(VkDevice _device, buf = _mesa_string_buffer_create(NULL, 1024); _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage)); + _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string); _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string); generate_shader_stats(device, variant, stage, buf);