X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=inline;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state.h;h=6a567688ee47b823e1196219877e83100bffa391;hb=4f4f477d6dd8ba5e0d37dbba50d28c1a85accf39;hp=c49b029d71a4282c12ddb472fceb4aa1024a0610;hpb=7708a864648aecd8aafb484ec7db18c2aba9e957;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index c49b029d71a..6a567688ee4 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -27,148 +27,264 @@ #ifndef SI_STATE_H #define SI_STATE_H -#include "radeonsi_pm4.h" +#include "si_pm4.h" +#include "radeon/r600_pipe_common.h" + +#define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1) +#define SI_MAX_ATTRIBS 16 + +struct si_screen; +struct si_shader; struct si_state_blend { struct si_pm4_state pm4; uint32_t cb_target_mask; - uint32_t cb_color_control; -}; - -struct si_state_viewport { - struct si_pm4_state pm4; - struct pipe_viewport_state viewport; + bool alpha_to_one; + bool dual_src_blend; }; struct si_state_rasterizer { struct si_pm4_state pm4; + /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */ + struct si_pm4_state pm4_poly_offset[3]; bool flatshade; bool two_side; + bool multisample_enable; + bool force_persample_interp; + bool line_stipple_enable; unsigned sprite_coord_enable; unsigned pa_sc_line_stipple; - unsigned pa_su_sc_mode_cntl; unsigned pa_cl_clip_cntl; - unsigned pa_cl_vs_out_cntl; - float offset_units; - float offset_scale; + unsigned clip_plane_enable; + bool poly_stipple_enable; + bool line_smooth; + bool poly_smooth; + bool uses_poly_offset; }; -struct si_state_dsa { - struct si_pm4_state pm4; - float alpha_ref; - unsigned alpha_func; - unsigned db_render_override; - unsigned db_render_control; +struct si_dsa_stencil_ref_part { uint8_t valuemask[2]; uint8_t writemask[2]; }; +struct si_state_dsa { + struct si_pm4_state pm4; + unsigned alpha_func; + struct si_dsa_stencil_ref_part stencil_ref; +}; + +struct si_stencil_ref { + struct r600_atom atom; + struct pipe_stencil_ref state; + struct si_dsa_stencil_ref_part dsa_part; +}; + struct si_vertex_element { unsigned count; - uint32_t rsrc_word3[PIPE_MAX_ATTRIBS]; - struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; + uint32_t rsrc_word3[SI_MAX_ATTRIBS]; + uint32_t format_size[SI_MAX_ATTRIBS]; + struct pipe_vertex_element elements[SI_MAX_ATTRIBS]; }; union si_state { struct { - struct si_pm4_state *sync; - struct si_pm4_state *init; struct si_state_blend *blend; - struct si_pm4_state *blend_color; - struct si_pm4_state *clip; - struct si_pm4_state *scissor; - struct si_state_viewport *viewport; - struct si_pm4_state *framebuffer; struct si_state_rasterizer *rasterizer; struct si_state_dsa *dsa; - struct si_pm4_state *fb_rs; - struct si_pm4_state *fb_blend; - struct si_pm4_state *dsa_stencil_ref; + struct si_pm4_state *poly_offset; + struct si_pm4_state *ls; + struct si_pm4_state *hs; + struct si_pm4_state *es; + struct si_pm4_state *gs; + struct si_pm4_state *vgt_shader_config; struct si_pm4_state *vs; - struct si_pm4_state *vs_sampler_views; - struct si_pm4_state *vs_sampler; - struct si_pm4_state *vs_const; struct si_pm4_state *ps; - struct si_pm4_state *ps_sampler_views; - struct si_pm4_state *ps_sampler; - struct si_pm4_state *ps_const; - struct si_pm4_state *spi; - struct si_pm4_state *vertex_buffers; - struct si_pm4_state *texture_barrier; - struct si_pm4_state *draw_info; - struct si_pm4_state *draw; } named; struct si_pm4_state *array[0]; }; +union si_state_atoms { + struct { + /* The order matters. */ + struct r600_atom *cache_flush; + struct r600_atom *streamout_begin; + struct r600_atom *streamout_enable; /* must be after streamout_begin */ + struct r600_atom *framebuffer; + struct r600_atom *msaa_sample_locs; + struct r600_atom *db_render_state; + struct r600_atom *msaa_config; + struct r600_atom *sample_mask; + struct r600_atom *cb_target_mask; + struct r600_atom *blend_color; + struct r600_atom *clip_regs; + struct r600_atom *clip_state; + struct r600_atom *shader_userdata; + struct r600_atom *scissors; + struct r600_atom *viewports; + struct r600_atom *stencil_ref; + struct r600_atom *spi_map; + struct r600_atom *spi_ps_input; + } s; + struct r600_atom *array[0]; +}; + +#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*)) + +struct si_shader_data { + struct r600_atom atom; + uint32_t sh_base[SI_NUM_SHADERS]; +}; + +#define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */ +#define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS +#define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1) + +/* User sampler views: 0..15 + * Polygon stipple tex: 16 + * FMASK sampler views: 17..33 (no sampler states) + */ +#define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS +#define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS) +#define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS + +/* User constant buffers: 0..15 + * Driver state constants: 16 + */ +#define SI_NUM_USER_CONST_BUFFERS 16 +#define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS +#define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1) + +/* Read-write buffer slots. + * + * Ring buffers: 0..1 + * Streamout buffers: 2..5 + */ +#define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */ +#define SI_RING_ESGS 0 /* for ES, GS */ +#define SI_RING_GSVS 1 /* for GS, VS */ +#define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */ +#define SI_RING_GSVS_2 3 +#define SI_RING_GSVS_3 4 +#define SI_NUM_RING_BUFFERS 5 +#define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS +#define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4) + +#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS + + +/* This represents descriptors in memory, such as buffer resources, + * image resources, and sampler states. + */ +struct si_descriptors { + /* The list of descriptors in malloc'd memory. */ + uint32_t *list; + /* The size of one descriptor. */ + unsigned element_dw_size; + /* The maximum number of descriptors. */ + unsigned num_elements; + /* Whether the list has been changed and should be re-uploaded. */ + bool list_dirty; + + /* The buffer where the descriptors have been uploaded. */ + struct r600_resource *buffer; + unsigned buffer_offset; + + /* The i-th bit is set if that element is enabled (non-NULL resource). */ + uint64_t enabled_mask; + + /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor + * array will be stored. */ + unsigned shader_userdata_offset; + /* Whether the pointer should be re-emitted. */ + bool pointer_dirty; +}; + +struct si_sampler_views { + struct si_descriptors desc; + struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS]; +}; + +struct si_sampler_states { + struct si_descriptors desc; + void *saved_states[2]; /* saved for u_blitter */ +}; + +struct si_buffer_resources { + struct si_descriptors desc; + enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */ + enum radeon_bo_priority priority; + struct pipe_resource **buffers; /* this has num_buffers elements */ +}; + #define si_pm4_block_idx(member) \ (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *)) -#define si_pm4_state_changed(rctx, member) \ - ((rctx)->queued.named.member != (rctx)->emitted.named.member) +#define si_pm4_state_changed(sctx, member) \ + ((sctx)->queued.named.member != (sctx)->emitted.named.member) -#define si_pm4_bind_state(rctx, member, value) \ +#define si_pm4_bind_state(sctx, member, value) \ do { \ - (rctx)->queued.named.member = (value); \ + (sctx)->queued.named.member = (value); \ } while(0) -#define si_pm4_delete_state(rctx, member, value) \ +#define si_pm4_delete_state(sctx, member, value) \ do { \ - if ((rctx)->queued.named.member == (value)) { \ - (rctx)->queued.named.member = NULL; \ + if ((sctx)->queued.named.member == (value)) { \ + (sctx)->queued.named.member = NULL; \ } \ - si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \ + si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \ si_pm4_block_idx(member)); \ } while(0) -#define si_pm4_set_state(rctx, member, value) \ - do { \ - if ((rctx)->queued.named.member != (value)) { \ - si_pm4_free_state(rctx, \ - (struct si_pm4_state *)(rctx)->queued.named.member, \ - si_pm4_block_idx(member)); \ - (rctx)->queued.named.member = (value); \ - } \ - } while(0) +/* si_descriptors.c */ +void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot, + struct pipe_resource *buffer, + unsigned stride, unsigned num_records, + bool add_tid, bool swizzle, + unsigned element_size, unsigned index_stride, uint64_t offset); +void si_init_all_descriptors(struct si_context *sctx); +bool si_upload_shader_descriptors(struct si_context *sctx); +void si_release_all_descriptors(struct si_context *sctx); +void si_all_descriptors_begin_new_cs(struct si_context *sctx); +void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer, + const uint8_t *ptr, unsigned size, uint32_t *const_offset); +void si_shader_change_notify(struct si_context *sctx); +void si_emit_shader_userdata(struct si_context *sctx, struct r600_atom *atom); /* si_state.c */ -struct si_pipe_shader_selector; +struct si_shader_selector; +void si_init_atom(struct si_context *sctx, struct r600_atom *atom, + struct r600_atom **list_elem, + void (*emit_func)(struct si_context *ctx, struct r600_atom *state)); boolean si_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, unsigned usage); -int si_shader_select(struct pipe_context *ctx, - struct si_pipe_shader_selector *sel, - unsigned *dirty); -void si_init_state_functions(struct r600_context *rctx); -void si_init_config(struct r600_context *rctx); - -/* si_state_streamout.c */ -struct pipe_stream_output_target * -si_create_so_target(struct pipe_context *ctx, - struct pipe_resource *buffer, - unsigned buffer_offset, - unsigned buffer_size); -void si_so_target_destroy(struct pipe_context *ctx, - struct pipe_stream_output_target *target); -void si_set_so_targets(struct pipe_context *ctx, - unsigned num_targets, - struct pipe_stream_output_target **targets, - unsigned append_bitmask); +void si_init_state_functions(struct si_context *sctx); +unsigned cik_bank_wh(unsigned bankwh); +unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode); +unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect); +unsigned cik_tile_split(unsigned tile_split); +unsigned si_array_mode(unsigned mode); +uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex); +unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil); +struct pipe_sampler_view * +si_create_sampler_view_custom(struct pipe_context *ctx, + struct pipe_resource *texture, + const struct pipe_sampler_view *state, + unsigned width0, unsigned height0, + unsigned force_level); + +/* si_state_shader.c */ +bool si_update_shaders(struct si_context *sctx); +void si_init_shader_functions(struct si_context *sctx); /* si_state_draw.c */ +void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom); void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo); - -/* si_commands.c */ -void si_cmd_context_control(struct si_pm4_state *pm4); -void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size, - uint64_t index_base, uint32_t index_count, - uint32_t initiator, bool predicate); -void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count, - uint32_t initiator, bool predicate); -void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl); +void si_trace_emit(struct si_context *sctx); #endif