X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=inline;f=src%2Fintel%2Fisl%2Fisl_surface_state.c;h=b22657e54c22d2340e1dea9906cd415175953fe3;hb=6c9f9a82d784701c9508fafa56182642cbfa544e;hp=323cf206d20c02d568d819941a15a9c8a16ca187;hpb=45cf049ba610f90476ddf2febff0634809ba0e1b;p=mesa.git diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 323cf206d20..b22657e54c2 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -27,7 +27,9 @@ #define __gen_user_data void static uint64_t -__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) +__gen_combine_address(__attribute__((unused)) void *data, + __attribute__((unused)) void *loc, uint64_t addr, + uint32_t delta) { return addr + delta; } @@ -82,7 +84,13 @@ static const uint32_t isl_to_gen_multisample_layout[] = { }; #endif -#if GEN_GEN >= 9 +#if GEN_GEN >= 12 +static const uint32_t isl_to_gen_aux_mode[] = { + [ISL_AUX_USAGE_NONE] = AUX_NONE, + [ISL_AUX_USAGE_MCS] = AUX_CCS_E, + [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, +}; +#elif GEN_GEN >= 9 static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_HIZ] = AUX_HIZ, @@ -259,16 +267,16 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * S3TC workaround that requires us to do reinterpretation. So assert * that they're at least the same bpb and block size. */ - MAYBE_UNUSED const struct isl_format_layout *surf_fmtl = + ASSERTED const struct isl_format_layout *surf_fmtl = isl_format_get_layout(info->surf->format); - MAYBE_UNUSED const struct isl_format_layout *view_fmtl = + ASSERTED const struct isl_format_layout *view_fmtl = isl_format_get_layout(info->surf->format); assert(surf_fmtl->bpb == view_fmtl->bpb); assert(surf_fmtl->bw == view_fmtl->bw); assert(surf_fmtl->bh == view_fmtl->bh); } - s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->view->format; + s.SurfaceFormat = info->view->format; #if GEN_GEN <= 5 s.ColorBufferComponentWriteDisables = info->write_disables; @@ -428,7 +436,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, /* For gen9 1-D textures, surface pitch is ignored */ s.SurfacePitch = 0; } else { - s.SurfacePitch = info->surf->row_pitch - 1; + s.SurfacePitch = info->surf->row_pitch_B - 1; } #if GEN_GEN >= 8 @@ -452,14 +460,21 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.RenderCacheReadWriteMode = 0; #endif - if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) { - s.CubeFaceEnablePositiveZ = 1; - s.CubeFaceEnableNegativeZ = 1; - s.CubeFaceEnablePositiveY = 1; - s.CubeFaceEnableNegativeY = 1; - s.CubeFaceEnablePositiveX = 1; - s.CubeFaceEnableNegativeX = 1; - } +#if GEN_GEN >= 11 + /* We've seen dEQP failures when enabling this bit with UINT formats, + * which particularly affects blorp_copy() operations. It shouldn't + * have any effect on UINT textures anyway, so disable it for them. + */ + s.EnableUnormPathInColorPipe = + !isl_format_has_int_channel(info->view->format); +#endif + + s.CubeFaceEnablePositiveZ = 1; + s.CubeFaceEnableNegativeZ = 1; + s.CubeFaceEnablePositiveY = 1; + s.CubeFaceEnableNegativeY = 1; + s.CubeFaceEnablePositiveX = 1; + s.CubeFaceEnableNegativeX = 1; #if GEN_GEN >= 6 s.NumberofMultisamples = ffs(info->surf->samples) - 1; @@ -470,42 +485,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if (GEN_GEN >= 8 || GEN_IS_HASWELL) - if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { - /* From the Sky Lake PRM Vol. 2d, - * RENDER_SURFACE_STATE::Shader Channel Select Red - * - * "For Render Target, Red, Green and Blue Shader Channel Selects - * MUST be such that only valid components can be swapped i.e. only - * change the order of components in the pixel. Any other values for - * these Shader Channel Select fields are not valid for Render - * Targets. This also means that there MUST not be multiple shader - * channels mapped to the same RT channel." - */ - assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED || - info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN || - info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE); - assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED || - info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN || - info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE); - assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED || - info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN || - info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE); - assert(info->view->swizzle.r != info->view->swizzle.g); - assert(info->view->swizzle.r != info->view->swizzle.b); - assert(info->view->swizzle.g != info->view->swizzle.b); - - /* From the Sky Lake PRM Vol. 2d, - * RENDER_SURFACE_STATE::Shader Channel Select Alpha - * - * "For Render Target, this field MUST be programmed to - * value = SCS_ALPHA." - */ - assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA); - } + if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle)); + s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; +#else + assert(isl_swizzle_is_identity(info->view->swizzle)); #endif s.SurfaceBaseAddress = info->address; @@ -563,7 +551,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, struct isl_tile_info tile_info; isl_surf_get_tile_info(info->aux_surf, &tile_info); uint32_t pitch_in_tiles = - info->aux_surf->row_pitch / tile_info.phys_extent_B.width; + info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width; s.AuxiliarySurfaceBaseAddress = info->aux_address; s.AuxiliarySurfacePitch = pitch_in_tiles - 1; @@ -605,7 +593,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } #endif -#if GEN_GEN >= 8 +#if GEN_GEN >= 8 && GEN_GEN < 11 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): * @@ -637,11 +625,44 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif if (info->aux_usage != ISL_AUX_USAGE_NONE) { -#if GEN_GEN >= 9 - s.RedClearColor = info->clear_color.u32[0]; - s.GreenClearColor = info->clear_color.u32[1]; - s.BlueClearColor = info->clear_color.u32[2]; - s.AlphaClearColor = info->clear_color.u32[3]; + if (info->use_clear_address) { +#if GEN_GEN >= 10 + s.ClearValueAddressEnable = true; + s.ClearValueAddress = info->clear_address; +#else + unreachable("Gen9 and earlier do not support indirect clear colors"); +#endif + } + +#if GEN_GEN == 11 + /* + * From BXML > GT > Shared Functions > vol5c Shared Functions > + * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable: + * + * Project: Gen11 + * + * "Enables Pixel backend hw to convert clear values into native format + * and write back to clear address, so that display and sampler can use + * the converted value for resolving fast cleared RTs." + * + * Summary: + * Clear color conversion must be enabled if the clear color is stored + * indirectly and fast color clears are enabled. + */ + if (info->use_clear_address) { + s.ClearColorConversionEnable = true; + } +#endif + +#if GEN_GEN >= 12 + assert(info->use_clear_address); +#elif GEN_GEN >= 9 + if (!info->use_clear_address) { + s.RedClearColor = info->clear_color.u32[0]; + s.GreenClearColor = info->clear_color.u32[1]; + s.BlueClearColor = info->clear_color.u32[2]; + s.AlphaClearColor = info->clear_color.u32[3]; + } #elif GEN_GEN >= 7 /* Prior to Sky Lake, we only have one bit for the clear color which * gives us 0 or 1 in whatever the surface's format happens to be. @@ -675,7 +696,27 @@ void isl_genX(buffer_fill_state_s)(void *state, const struct isl_buffer_fill_state_info *restrict info) { - uint32_t num_elements = info->size / info->stride; + uint64_t buffer_size = info->size_B; + + /* Uniform and Storage buffers need to have surface size not less that the + * aligned 32-bit size of the buffer. To calculate the array lenght on + * unsized arrays in StorageBuffer the last 2 bits store the padding size + * added to the surface, so we can calculate latter the original buffer + * size to know the number of elements. + * + * surface_size = isl_align(buffer_size, 4) + + * (isl_align(buffer_size) - buffer_size) + * + * buffer_size = (surface_size & ~3) - (surface_size & 3) + */ + if (info->format == ISL_FORMAT_RAW || + info->stride_B < isl_format_get_layout(info->format)->bpb / 8) { + assert(info->stride_B == 1); + uint64_t aligned_size = isl_align(buffer_size, 4); + buffer_size = aligned_size + (aligned_size - buffer_size); + } + + uint32_t num_elements = buffer_size / info->stride_B; if (GEN_GEN >= 7) { /* From the IVB PRM, SURFACE_STATE::Height, @@ -698,7 +739,7 @@ isl_genX(buffer_fill_state_s)(void *state, struct GENX(RENDER_SURFACE_STATE) s = { 0, }; s.SurfaceType = SURFTYPE_BUFFER; - s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->format; + s.SurfaceFormat = info->format; #if GEN_GEN >= 6 s.SurfaceVerticalAlignment = isl_to_gen_valign[4]; @@ -718,7 +759,7 @@ isl_genX(buffer_fill_state_s)(void *state, s.Depth = ((num_elements - 1) >> 20) & 0x7f; #endif - s.SurfacePitch = info->stride - 1; + s.SurfacePitch = info->stride_B - 1; #if GEN_GEN >= 6 s.NumberofMultisamples = MULTISAMPLECOUNT_1; @@ -742,10 +783,10 @@ isl_genX(buffer_fill_state_s)(void *state, #endif #if (GEN_GEN >= 8 || GEN_IS_HASWELL) - s.ShaderChannelSelectRed = SCS_RED; - s.ShaderChannelSelectGreen = SCS_GREEN; - s.ShaderChannelSelectBlue = SCS_BLUE; - s.ShaderChannelSelectAlpha = SCS_ALPHA; + s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; + s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g; + s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b; + s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a; #endif GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); @@ -756,15 +797,33 @@ isl_genX(null_fill_state)(void *state, struct isl_extent3d size) { struct GENX(RENDER_SURFACE_STATE) s = { .SurfaceType = SURFTYPE_NULL, - .SurfaceFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_B8G8R8A8_UNORM, + /* We previously had this format set to B8G8R8A8_UNORM but ran into + * hangs on IVB. R32_UINT seems to work for everybody. + * + * https://gitlab.freedesktop.org/mesa/mesa/issues/1872 + */ + .SurfaceFormat = ISL_FORMAT_R32_UINT, #if GEN_GEN >= 7 - .SurfaceArray = size.depth > 0, + .SurfaceArray = size.depth > 1, #endif #if GEN_GEN >= 8 .TileMode = YMAJOR, #else .TiledSurface = true, .TileWalk = TILEWALK_YMAJOR, +#endif +#if GEN_GEN == 7 + /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared + * Functions" + * + * RENDER_SURFACE_STATE::Surface Vertical Alignment + * + * "This field must be set to VALIGN_4 for all tiled Y Render Target + * surfaces." + * + * Affect IVB, HSW. + */ + .SurfaceVerticalAlignment = VALIGN_4, #endif .Width = size.width - 1, .Height = size.height - 1,