X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=inline;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_meta_fast_clear.c;h=f5ecbb5498981f02e0986fa6ebe80dd93b9eec89;hb=8765f1d7ddfb00dc5b202e4e679ebe640a547d50;hp=b4e75a76bd1ad5614cc109355c4367b58b7224d4;hpb=2d6d3461d307636b61d0f483677aaad11d1fd42a;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index b4e75a76bd1..f5ecbb54989 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c @@ -128,7 +128,7 @@ brw_bind_rep_write_shader(struct brw_context *brw, float *color) _mesa_AttachShader(clear->shader_prog, vs); _mesa_DeleteShader(vs); _mesa_BindAttribLocation(clear->shader_prog, 0, "position"); - _mesa_ObjectLabel(GL_PROGRAM, clear->shader_prog, -1, "meta clear"); + _mesa_ObjectLabel(GL_PROGRAM, clear->shader_prog, -1, "meta repclear"); _mesa_LinkProgram(clear->shader_prog); clear->color_location = @@ -200,7 +200,7 @@ brw_draw_rectlist(struct gl_context *ctx, struct rect *rect, int num_instances) brw_draw_prims(ctx, &prim, 1, NULL, GL_TRUE, start, start + count - 1, - NULL, NULL); + NULL, 0, NULL); } static void @@ -339,11 +339,16 @@ is_color_fast_clear_compatible(struct brw_context *brw, mesa_format format, const union gl_color_union *color) { - if (_mesa_is_format_integer_color(format)) + if (_mesa_is_format_integer_color(format)) { + if (brw->gen >= 8) { + perf_debug("Integer fast clear not enabled for (%s)", + _mesa_get_format_name(format)); + } return false; + } for (int i = 0; i < 4; i++) { - if (color->f[i] != 0.0 && color->f[i] != 1.0 && + if (color->f[i] != 0.0f && color->f[i] != 1.0f && _mesa_format_has_color_component(format, i)) { return false; } @@ -361,7 +366,7 @@ compute_fast_clear_color_bits(const union gl_color_union *color) uint32_t bits = 0; for (int i = 0; i < 4; i++) { /* Testing for non-0 works for integer and float colors */ - if (color->f[i] != 0.0) + if (color->f[i] != 0.0f) bits |= 1 << (GEN7_SURFACE_CLEAR_COLOR_SHIFT + (3 - i)); } return bits; @@ -376,7 +381,7 @@ set_fast_clear_op(struct brw_context *brw, uint32_t op) * 3DSTATE_PS. */ brw->wm.fast_clear_op = op; - brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; + brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM; } static void @@ -400,8 +405,8 @@ use_rectlist(struct brw_context *brw, bool enable) * _NEW_BUFFERS to make sure we emit new SURFACE_STATE with the new fast * clear color value. */ - brw->state.dirty.mesa |= _NEW_LIGHT | _NEW_BUFFERS; - brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; + brw->NewGLState |= _NEW_LIGHT | _NEW_BUFFERS; + brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM; } bool @@ -466,7 +471,8 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb, * linear (untiled) memory is UNDEFINED." */ if (irb->mt->tiling == I915_TILING_NONE) { - perf_debug("falling back to plain clear because buffers are untiled\n"); + perf_debug("Falling back to plain clear because %dx%d buffer is untiled\n", + irb->mt->logical_width0, irb->mt->logical_height0); clear_type = PLAIN_CLEAR; } @@ -477,7 +483,8 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb, for (int i = 0; i < 4; i++) { if (_mesa_format_has_color_component(irb->mt->format, i) && !color_mask[i]) { - perf_debug("falling back to plain clear because of color mask\n"); + perf_debug("Falling back to plain clear on %dx%d buffer because of color mask\n", + irb->mt->logical_width0, irb->mt->logical_height0); clear_type = PLAIN_CLEAR; } } @@ -602,7 +609,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb, * color before resolve and sets irb->mt->fast_clear_state to UNRESOLVED if * we render to it. */ - brw->state.dirty.mesa |= _NEW_BUFFERS; + brw->NewGLState |= _NEW_BUFFERS; /* Set the custom state back to normal and dirty the same bits as above */ @@ -616,7 +623,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb, * write-flush must be issued before sending any DRAW commands on that * render target. */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); /* If we had to fall back to plain clear for any buffers, clear those now * by calling into meta. @@ -643,11 +650,14 @@ get_resolve_rect(struct brw_context *brw, * The scaledown factors in the table that follows are related to the * alignment size returned by intel_get_non_msrt_mcs_alignment() by a * multiplier. For IVB and HSW, we divide by two, for BDW we multiply - * by 8 and 16. + * by 8 and 16 and 8 and 8 for SKL. */ intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align); - if (brw->gen >= 8) { + if (brw->gen >= 9) { + x_scaledown = x_align * 8; + y_scaledown = y_align * 8; + } else if (brw->gen >= 8) { x_scaledown = x_align * 8; y_scaledown = y_align * 16; } else { @@ -667,7 +677,7 @@ brw_meta_resolve_color(struct brw_context *brw, GLuint fbo, rbo; struct rect rect; - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); _mesa_meta_begin(ctx, MESA_META_ALL);