X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=Cesar_Strauss.mdwn;h=fa2b1fb7c98731d1db712191dfa26ae0ac56db87;hb=454db4a2971df843168de033bd27c517a935a806;hp=1d073ec3cfcd691975d60c7e4aa54821e98da388;hpb=8533eab8147061afea223350262e1ed88bec8b4f;p=libreriscv.git

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 Contributor
 
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=cestrauss@gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
+
 # Status Tracking
 
 ## Currently working on
 
-* <https://bugs.libre-soc.org/show_bug.cgi?id=318>
-	* fix LDSTCompUnit
+1. ALU CompUnit needs to recognise that RA (src1) can be zero  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=336>  
+	Status: DONE  
+	Unit test Status: in progress
+
+
+2. Something about the above (5), being optional.  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=336#c5>  
+	Status: DONE  
+	Unit test Status: in progress
+
+3. CompALUMulti parallel functions unit test  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=336#c11>  
+	Priority: Medium-to-High
+
+4. Code-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=318#c18>  
+	Status: Need a review of Luke's implementation, compared to mine.  
+	Priority: Low
+
+5. Test dual ports (two L0CacheBuffer with two ports, 4-4 as well) which
+write to the same memory  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=318#c11>  
+	Status: not started  
+	Priority: High
+
+6. Luke tried two LDs in the score6600 code - they failed.  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=318#c17>  
+	Status: not started, need to check the [prototype] L0CacheBuffer  
+	Priority: High
+
+7. Fix a bug in the LDSTCompUnit  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=318>  
+	Status: Luke thinks he fixed it, but needs a review and improving the
+unit tests.   
+	See: <https://bugs.libre-soc.org/show_bug.cgi?id=318#c7>  
+	Priority: Medium
+
+8. LDSTCompUnit parallel functions unit test  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=350>  
+	Priority: Medium-ish
+
+9. FSM-based ALU example needed (compliant with ALU CompUnit)  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=417>  
+	Status: DONE  
+	Investigating one last optimization opportunity.  
+	Priority: Low
+	
+10. Find root cause of cxxsim hang  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=475#c2>  
+	Status: ongoing  
+	Priority: High
+
+## Completed but not yet submitted:
+
+## Submitted for NLNet RFP
+
+## Paid