X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=The_Mission.mdwn;h=ca46581956ae735421de4209b44976ab86b7a7aa;hb=ada035ea5ed6e35b2324dfbcf2783377eb252e3f;hp=81c3585955918250ce4f9de7343945141f8e7cee;hpb=343310b4f3e6ba6fbc631762c9c5e5510ac747cd;p=libreriscv.git diff --git a/The_Mission.mdwn b/The_Mission.mdwn index 81c358595..ca4658195 100644 --- a/The_Mission.mdwn +++ b/The_Mission.mdwn @@ -1,20 +1,58 @@ +# Trustable Hardware - - give mass volume appliance manufacturers an alternative to expensive un-auditable chips. - - maximize the degree of trust a customer can place in their processor. +> We believe a computer should be safe to use, and this starts with a +> safe processor. -## The Means: +# The Mission -provide the customer the **freedom to study, modify, and redistribute** the full SoC source from HDL and boot loader to down to the VLSI. +- to provide a libre, secure and transparently developed hybrid CPU VPU + GPU architecture to the world. +- to maximize the degree of trust a customer or user can place in + products using our processor designs. +- through significantly reduced product development costs and time to + market, incentivise mass volume appliance manufacturers to ensure + that end-users of their products enjoy the same level of access to + full Board Support Package source code and Reference Designs that + they have, including for the processor hardware design. +- to disincentivise Tivoisation, the deployment of DRM and other lockout + techniques that interfere with end-user trust in the products that + they legitimately own. -## The Market: +To accomplish this we: + +- use collaborative techniques +- operate entirely transparently +- invite developers and experts around the world to contribute without NDAs +- invite inventors to contribute relevant patents to patent pools (OIN) + +# The Means: + +- provide the customer the **freedom to study, modify, and redistribute** + the full SoC source, from HDL, through BIOS, boot loader, to drivers and OS. +- engage in **full transparency** at every level of the development, + right from the inception through to delivery of silicon. no exceptions. +- listen to **constructive input** from world-leading industry experts, + engineers and enthusiasts alike, in real-time, without NDAs creating + artificial barriers to communication and hampering success. + +# The Market: - chromebooks - smartphones - tablets - industrial boards - single-board computers (like the Raspberry Pi) + - wearables + - CV capable flight controller for lightweight drones - whatever you want -## The Machine: +# The Products: + +- our first target (Dec 2020): a single-core dual-issue 180nm 64-bit + "demo" QFP chip that will also be a saleable product in the "Embedded" + space (Arduino, STM32F, Ingenic jz4720). +- a full quad core SoC: 800mhz, dual issue, 4-wide FP32, Hybrid CPU / + GPU / VPU [and later an ML inference core], comparable to the Allwinner + 64 in capability. +- Products based on customer - and client - driven needs and requirements -a (quad core, 800mhz, dual issue, 4-wide FP32, CPU, GPU, VPU, [and later an ML inference core] ) SOC.