X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=cole.mdwn;h=dbc8a7154dd5481205f031e9b32afde2293c4d1f;hb=19fd0901f92d28f3bd199a11229ff4c1d39e3af7;hp=eb9246cad5ca024773de0bf3ad6d5e4ecb4343ba;hpb=16782dd0d7d58ec102edd5631f73533e4c7dfc32;p=libreriscv.git

diff --git a/cole.mdwn b/cole.mdwn
index eb9246cad..dbc8a7154 100644
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -10,6 +10,18 @@ move things along from one stage to the next
 
 ## Currently working on
 
+- Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
+  - shared with lkcl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
@@ -30,22 +42,47 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted
 
-- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
+## Submitted for NLNet RFP
 
-- Coriolis2 documentation and setup scripts
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
+submitted but not confirmed paid:
 
-- TRAP pipeline discussion
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=138>
+## Paid
 
-## Submitted for NLNet RFP
+### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5
 
-submitted but not confirmed paid:
+- <https://bugs.libre-soc.org/show_bug.cgi?id=502> determine SRAM block size and implement it 
+  - EUR 50
 
-### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
+### MOU wishbone 2019-10-043, received payment on 2021-MAY-5
 
-## Paid
+- <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
+  - EUR 150
+
+### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=178> Coriolis2 tutorial
+  - EUR 500
+
+### MOU wishbone 2019-10-043, received payment on 2020-OCT-01
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
+  - EUR 150
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
+  - EUR 100
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver 
+  - EUR 100
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
+  - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
+  - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
+
+### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01
+
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>