X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=dev%2Fsinic.cc;h=363994919c8c95da50393ec05402ca90505c9b7c;hb=9e3d79694ca9e204bcbfa9c197db17b581dc7a29;hp=6ffd0a664e8f5f6b688054b1081ec987e14bc297;hpb=c22664845900727493097e961d2bc17fd9c60372;p=gem5.git diff --git a/dev/sinic.cc b/dev/sinic.cc index 6ffd0a664..363994919 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -47,7 +47,7 @@ #include "sim/eventq.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace Net; using namespace TheISA; @@ -113,8 +113,6 @@ Device::Device(Params *p) p->dma_no_allocate); } else if (p->payload_bus) panic("must define a header bus if defining a payload bus"); - - pioDelayWrite = p->pio_delay_write && pioInterface; } Device::~Device() @@ -353,35 +351,32 @@ Device::prepareRead(int cpu, int index) void Device::prepareWrite(int cpu, int index) { - if (cpu >= writeQueue.size()) - writeQueue.resize(cpu + 1); - prepareIO(cpu, index); } /** * I/O read of device register */ -Fault * +Fault Device::read(MemReqPtr &req, uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault * fault = readBar(req, data); + Fault fault = readBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; } -Fault * +Fault Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; + int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -428,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) /** * IPR read of device register */ -Fault * +Fault Device::iprRead(Addr daddr, int cpu, uint64_t &result) { if (!regValid(daddr)) @@ -458,26 +453,26 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result) /** * I/O write of device register */ -Fault * +Fault Device::write(MemReqPtr &req, const uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault * fault = writeBar(req, data); + Fault fault = writeBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; } -Fault * +Fault Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; + int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -494,34 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - //uint32_t reg32 = *(uint32_t *)data; + uint32_t reg32 = *(uint32_t *)data; uint64_t reg64 = *(uint64_t *)data; + VirtualReg &vnic = virtualRegs[index]; + DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr, - req->paddr, req->vaddr, req->size); + info.name, cpu, info.size == 4 ? reg32 : reg64, + daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); - if (pioDelayWrite) - writeQueue[cpu].push_back(RegWriteData(daddr, reg64)); - - if (!pioDelayWrite || !info.delay_write) - regWrite(daddr, cpu, data); - - return NoFault; -} - -void -Device::regWrite(Addr daddr, int cpu, const uint8_t *data) -{ - Addr index = daddr >> Regs::VirtualShift; - Addr raddr = daddr & Regs::VirtualMask; - - uint32_t reg32 = *(uint32_t *)data; - uint64_t reg64 = *(uint64_t *)data; - VirtualReg &vnic = virtualRegs[index]; - switch (raddr) { case Regs::Config: changeConfig(reg32); @@ -568,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data) } break; } + + return NoFault; } void @@ -781,6 +761,8 @@ Device::reset() regs.Config |= Config_RxThread; if (params()->tx_thread) regs.Config |= Config_TxThread; + if (params()->rss) + regs.Config |= Config_RSS; regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow; regs.RxMaxCopy = params()->rx_max_copy; regs.TxMaxCopy = params()->tx_max_copy; @@ -1571,27 +1553,6 @@ Device::cacheAccess(MemReqPtr &req) DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n", req->cmd.toString(), req->paddr, bar, daddr); - if (!pioDelayWrite || !req->cmd.isWrite()) - return curTick + pioLatency; - - if (bar == 0) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; - std::list &wq = writeQueue[cpu]; - if (wq.empty()) - panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr); - - const RegWriteData &data = wq.front(); - if (data.daddr != daddr) - panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x", - cpu, data.daddr, daddr); - - const Regs::Info &info = regInfo(data.daddr); - if (info.delay_write) - regWrite(daddr, cpu, (uint8_t *)&data.value); - - wq.pop_front(); - } - return curTick + pioLatency; } @@ -1649,7 +1610,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param dma_write_factor; Param dma_no_allocate; Param pio_latency; - Param pio_delay_write; Param intr_delay; Param rx_delay; @@ -1666,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param hardware_address; Param rx_thread; Param tx_thread; + Param rss; END_DECLARE_SIM_OBJECT_PARAMS(Device) @@ -1693,7 +1654,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(dma_write_factor, "multiplier for dma writes"), INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"), INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"), - INIT_PARAM(pio_delay_write, ""), INIT_PARAM(intr_delay, "Interrupt Delay"), INIT_PARAM(rx_delay, "Receive Delay"), @@ -1709,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(Device) @@ -1741,7 +1702,6 @@ CREATE_SIM_OBJECT(Device) params->dma_write_factor = dma_write_factor; params->dma_no_allocate = dma_no_allocate; params->pio_latency = pio_latency; - params->pio_delay_write = pio_delay_write; params->intr_delay = intr_delay; params->tx_delay = tx_delay; @@ -1758,6 +1718,7 @@ CREATE_SIM_OBJECT(Device) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new Device(params); }