X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=dev%2Fsinic.cc;h=a9363954b21c26996a6adf8be14c9cfd5a4e87e1;hb=d207168eda13483a2990cdf060c1a7ead42cc9da;hp=829d58d32c2e91a6facec4b8d0e4c18d9d836309;hpb=0e4a80df1a471671b6ef7003e29124b6835ade42;p=gem5.git

diff --git a/dev/sinic.cc b/dev/sinic.cc
index 829d58d32..a9363954b 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -113,8 +113,6 @@ Device::Device(Params *p)
                                                  p->dma_no_allocate);
     } else if (p->payload_bus)
         panic("must define a header bus if defining a payload bus");
-
-    pioDelayWrite = p->pio_delay_write && pioInterface;
 }
 
 Device::~Device()
@@ -353,20 +351,17 @@ Device::prepareRead(int cpu, int index)
 void
 Device::prepareWrite(int cpu, int index)
 {
-    if (cpu >= writeQueue.size())
-        writeQueue.resize(cpu + 1);
-
     prepareIO(cpu, index);
 }
 
 /**
  * I/O read of device register
  */
-Fault *
+Fault
 Device::read(MemReqPtr &req, uint8_t *data)
 {
     assert(config.command & PCI_CMD_MSE);
-    Fault * fault = readBar(req, data);
+    Fault fault = readBar(req, data);
 
     if (fault == MachineCheckFault) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@@ -378,7 +373,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
     return fault;
 }
 
-Fault *
+Fault
 Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
 {
     int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@@ -428,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
 /**
  * IPR read of device register
  */
-Fault *
+Fault
 Device::iprRead(Addr daddr, int cpu, uint64_t &result)
 {
     if (!regValid(daddr))
@@ -458,11 +453,11 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
 /**
  * I/O write of device register
  */
-Fault *
+Fault
 Device::write(MemReqPtr &req, const uint8_t *data)
 {
     assert(config.command & PCI_CMD_MSE);
-    Fault * fault = writeBar(req, data);
+    Fault fault = writeBar(req, data);
 
     if (fault == MachineCheckFault) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@@ -474,7 +469,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
     return fault;
 }
 
-Fault *
+Fault
 Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
 {
     int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@@ -496,6 +491,8 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
 
     uint32_t reg32 = *(uint32_t *)data;
     uint64_t reg64 = *(uint64_t *)data;
+    VirtualReg &vnic = virtualRegs[index];
+
     DPRINTF(EthernetPIO,
             "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
             info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
@@ -503,25 +500,6 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
 
     prepareWrite(cpu, index);
 
-    if (pioDelayWrite)
-        writeQueue[cpu].push_back(RegWriteData(daddr, reg64));
-
-    if (!pioDelayWrite || !info.delay_write)
-        regWrite(daddr, cpu, data);
-
-    return NoFault;
-}
-
-void
-Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
-{
-    Addr index = daddr >> Regs::VirtualShift;
-    Addr raddr = daddr & Regs::VirtualMask;
-
-    uint32_t reg32 = *(uint32_t *)data;
-    uint64_t reg64 = *(uint64_t *)data;
-    VirtualReg &vnic = virtualRegs[index];
-
     switch (raddr) {
       case Regs::Config:
         changeConfig(reg32);
@@ -568,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
         }
         break;
     }
+
+    return NoFault;
 }
 
 void
@@ -1571,27 +1551,6 @@ Device::cacheAccess(MemReqPtr &req)
     DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n",
             req->cmd.toString(), req->paddr, bar, daddr);
 
-    if (!pioDelayWrite || !req->cmd.isWrite())
-        return curTick + pioLatency;
-
-    if (bar == 0) {
-        int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
-        std::list<RegWriteData> &wq = writeQueue[cpu];
-        if (wq.empty())
-            panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
-
-        const RegWriteData &data = wq.front();
-        if (data.daddr != daddr)
-            panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
-                  cpu, data.daddr, daddr);
-
-        const Regs::Info &info = regInfo(data.daddr);
-        if (info.delay_write)
-            regWrite(daddr, cpu, (uint8_t *)&data.value);
-
-        wq.pop_front();
-    }
-
     return curTick + pioLatency;
 }
 
@@ -1649,7 +1608,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
     Param<Tick> dma_write_factor;
     Param<bool> dma_no_allocate;
     Param<Tick> pio_latency;
-    Param<bool> pio_delay_write;
     Param<Tick> intr_delay;
 
     Param<Tick> rx_delay;
@@ -1693,7 +1651,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
     INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
     INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
     INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
-    INIT_PARAM(pio_delay_write, ""),
     INIT_PARAM(intr_delay, "Interrupt Delay"),
 
     INIT_PARAM(rx_delay, "Receive Delay"),
@@ -1741,7 +1698,6 @@ CREATE_SIM_OBJECT(Device)
     params->dma_write_factor = dma_write_factor;
     params->dma_no_allocate = dma_no_allocate;
     params->pio_latency = pio_latency;
-    params->pio_delay_write = pio_delay_write;
     params->intr_delay = intr_delay;
 
     params->tx_delay = tx_delay;