X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=riscv%2Finteractive.cc;h=b645c29e1c80a81b69a2bfea624deae41bd2eb40;hb=4856220f05094a870e9544523428b85ec597fd42;hp=dbcd22455d5fe6fdb75388946df176d7227ca6df;hpb=f8a83a80525264761a982cdb4074cb09ac72d7de;p=riscv-isa-sim.git diff --git a/riscv/interactive.cc b/riscv/interactive.cc index dbcd224..b645c29 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -168,7 +168,7 @@ reg_t sim_t::get_pc(const std::vector& args) throw trap_interactive(); processor_t *p = get_core(args[0]); - return p->state.pc; + return p->get_state()->pc; } void sim_t::interactive_pc(const std::string& cmd, const std::vector& args) @@ -198,7 +198,7 @@ reg_t sim_t::get_reg(const std::vector& args) if (r >= NXPR) throw trap_interactive(); - return p->state.XPR[r]; + return p->get_state()->XPR[r]; } freg_t sim_t::get_freg(const std::vector& args) @@ -213,7 +213,7 @@ freg_t sim_t::get_freg(const std::vector& args) if (r >= NFPR) throw trap_interactive(); - return p->state.FPR[r]; + return p->get_state()->FPR[r]; } void sim_t::interactive_reg(const std::string& cmd, const std::vector& args) @@ -223,7 +223,7 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vectorstate.XPR[r]); + fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->get_state()->XPR[r]); if ((r + 1) % 4 == 0) fprintf(stderr, "\n"); }