X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=riscv%2Fprocessor.h;h=5557e5afad3bceede99d44735142e9bd6793df6b;hb=a9c5b05eca6a46a0c8722b26b741fc7f1de22405;hp=f3b2f62cd69443d1eaa0c3cfd1fbb351143ebb3c;hpb=b189b9b128ce619f9423009062a85ccb17b32db9;p=riscv-isa-sim.git diff --git a/riscv/processor.h b/riscv/processor.h index f3b2f62..5557e5a 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -1,107 +1,154 @@ // See LICENSE for license details. - #ifndef _RISCV_PROCESSOR_H #define _RISCV_PROCESSOR_H #include "decode.h" -#include -#include "trap.h" #include "config.h" - -#define MAX_UTS 2048 +#include "devices.h" +#include +#include +#include class processor_t; class mmu_t; typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t); class sim_t; +class trap_t; +class extension_t; +class disassembler_t; -// this class represents one processor in a RISC-V machine. -class processor_t +struct insn_desc_t { -public: - processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id); - ~processor_t(); + insn_bits_t match; + insn_bits_t mask; + insn_func_t rv32; + insn_func_t rv64; +}; - void reset(bool value); - void step(size_t n, bool noisy); // run for n cycles - void deliver_ipi(); // register an interprocessor interrupt - bool running() { return run; } - void set_pcr(int which, reg_t val); - void set_interrupt(int which, bool on); - reg_t get_pcr(int which); - mmu_t* get_mmu() { return &mmu; } +struct commit_log_reg_t +{ + reg_t addr; + reg_t data; +}; -private: - sim_t& sim; - mmu_t& mmu; // main memory is always accessed via the mmu +// architectural state of a RISC-V hart +struct state_t +{ + void reset(); - // user-visible architected state + reg_t pc; regfile_t XPR; regfile_t FPR; - reg_t pc; - reg_t cycle; - - // privileged control registers - reg_t epc; - reg_t badvaddr; - reg_t evec; - reg_t pcr_k0; - reg_t pcr_k1; - reg_t cause; + + // control and status registers + reg_t prv; + reg_t mstatus; + reg_t mepc; + reg_t mbadaddr; + reg_t mscratch; + reg_t mcause; + reg_t minstret; + reg_t mie; + reg_t mip; + reg_t medeleg; + reg_t mideleg; + reg_t mucounteren; + reg_t mscounteren; + reg_t sepc; + reg_t sbadaddr; + reg_t sscratch; + reg_t stvec; + reg_t sptbr; + reg_t scause; reg_t tohost; reg_t fromhost; - uint32_t id; - uint32_t sr; // only modify the status register using set_pcr() - uint32_t fsr; - uint32_t count; - uint32_t compare; + uint32_t fflags; + uint32_t frm; + bool serialized; // whether timer CSRs are in a well-defined state - bool run; // !reset + reg_t load_reservation; - // functions - void take_interrupt(); // take a trap if any interrupts are pending - void set_fsr(uint32_t val); // set the floating-point status register - void take_trap(reg_t t, bool noisy); // take an exception - void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction +#ifdef RISCV_ENABLE_COMMITLOG + commit_log_reg_t log_reg_write; + reg_t last_inst_priv; +#endif +}; - // vector stuff - void vcfg(); - void setvl(int vlapp); +// this class represents one processor in a RISC-V machine. +class processor_t : public abstract_device_t +{ +public: + processor_t(const char* isa, sim_t* sim, uint32_t id); + ~processor_t(); - reg_t vecbanks; - uint32_t vecbanks_count; + void set_debug(bool value); + void set_histogram(bool value); + void reset(bool value); + void step(size_t n); // run for n cycles + bool running() { return run; } + void set_csr(int which, reg_t val); + void raise_interrupt(reg_t which); + reg_t get_csr(int which); + mmu_t* get_mmu() { return mmu; } + state_t* get_state() { return &state; } + extension_t* get_extension() { return ext; } + bool supports_extension(unsigned char ext) { + if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a'; + return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1); + } + void set_privilege(reg_t); + void yield_load_reservation() { state.load_reservation = (reg_t)-1; } + void update_histogram(reg_t pc); + + void register_insn(insn_desc_t); + void register_extension(extension_t*); + + // MMIO slave interface + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); - bool utmode; - uint32_t utidx; - int vlmax; - int vl; - int nxfpr_bank; - int nxpr_use; - int nfpr_use; - processor_t* uts[MAX_UTS]; +private: + sim_t* sim; + mmu_t* mmu; // main memory is always accessed via the mmu + extension_t* ext; + disassembler_t* disassembler; + state_t state; + uint32_t id; + unsigned max_xlen; + unsigned xlen; + reg_t isa; + std::string isa_string; + bool run; // !reset + bool debug; + bool histogram_enabled; + + std::vector instructions; + std::map pc_histogram; - // this constructor is used for each of the uts - processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx); + static const size_t OPCODE_CACHE_SIZE = 8191; + insn_desc_t opcode_cache[OPCODE_CACHE_SIZE]; + + void check_timer(); + void take_interrupt(); // take a trap if any interrupts are pending + void take_trap(trap_t& t, reg_t epc); // take an exception + void disasm(insn_t insn); // disassemble and print an instruction friend class sim_t; friend class mmu_t; - friend class htif_isasim_t; + friend class rtc_t; + friend class extension_t; - #include "dispatch.h" + void parse_isa_string(const char* isa); + void build_opcode_map(); + void register_base_instructions(); + insn_func_t decode_insn(insn_t insn); }; -#ifndef RISCV_ENABLE_RVC -# define set_pc(x) \ - do { if((x) & (sizeof(insn_t)-1)) \ - { badvaddr = (x); throw trap_instruction_address_misaligned; } \ - npc = (x); \ - } while(0) -#else -# define set_pc(x) \ - do { if((x) & ((sr & SR_EC) ? 1 : 3)) \ - { badvaddr = (x); throw trap_instruction_address_misaligned; } \ - npc = (x); \ - } while(0) -#endif +reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); + +#define REGISTER_INSN(proc, name, match, mask) \ + extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \ + extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \ + proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name}); #endif