X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=sim%2Ffrv%2Fprofile.c;h=89332e580402ec24b62b746ec80f6593c0598a77;hb=e7954ef5e5ed90fb7d28c013518f4c2e6bcd20a1;hp=441590eb581d66d4b31c337fb38a334c326cf675;hpb=32a046ab0d7717256f16f59d87438474e825fcb8;p=binutils-gdb.git

diff --git a/sim/frv/profile.c b/sim/frv/profile.c
index 441590eb581..89332e58040 100644
--- a/sim/frv/profile.c
+++ b/sim/frv/profile.c
@@ -16,9 +16,11 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* This must come before any other includes.  */
+#include "defs.h"
 
-*/
 #define WANT_CPU
 #define WANT_CPU_FRVBF
 
@@ -899,7 +901,7 @@ wait_for_flush (SIM_CPU *cpu)
     }
   if (TRACE_INSN_P (cpu) && wait)
     {
-      sprintf (hazard_name, "Data cache flush address %p:", address);
+      sprintf (hazard_name, "Data cache flush address %x:", address);
       frv_model_trace_wait_cycles (cpu, wait, hazard_name);
     }
 }
@@ -1010,7 +1012,7 @@ frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
     }
 }
 
-USI
+void
 frvbf_model_branch (SIM_CPU *current_cpu, PCADDR target, int hint)
 {
   /* Record the hint and branch address for use in profiling.  */
@@ -1785,7 +1787,7 @@ enforce_full_fr_latency (SIM_CPU *cpu, INT in_FR)
 
 /* Calculate how long the post processing for a floating point insn must
    wait for resources to become available.  */
-int
+void
 post_wait_for_FR (SIM_CPU *cpu, INT in_FR)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1801,7 +1803,7 @@ post_wait_for_FR (SIM_CPU *cpu, INT in_FR)
 
 /* Calculate how long the post processing for a floating point insn must
    wait for resources to become available.  */
-int
+void
 post_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1824,7 +1826,7 @@ post_wait_for_FRdouble (SIM_CPU *cpu, INT in_FR)
     }
 }
 
-int
+void
 post_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1838,7 +1840,7 @@ post_wait_for_ACC (SIM_CPU *cpu, INT in_ACC)
     }
 }
 
-int
+void
 post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1857,7 +1859,7 @@ post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR)
     }
 }
 
-int
+void
 post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1871,7 +1873,7 @@ post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
     }
 }
 
-int
+void
 post_wait_for_fdiv (SIM_CPU *cpu, INT slot)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1889,7 +1891,7 @@ post_wait_for_fdiv (SIM_CPU *cpu, INT slot)
     }
 }
 
-int
+void
 post_wait_for_fsqrt (SIM_CPU *cpu, INT slot)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1907,7 +1909,7 @@ post_wait_for_fsqrt (SIM_CPU *cpu, INT slot)
     }
 }
 
-int
+void
 post_wait_for_float (SIM_CPU *cpu, INT slot)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
@@ -1925,7 +1927,7 @@ post_wait_for_float (SIM_CPU *cpu, INT slot)
     }
 }
 
-int
+void
 post_wait_for_media (SIM_CPU *cpu, INT slot)
 {
   FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);